Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A data processing system, the data processing system comprising: a local interleaver circuit operable to: receive a data input that includes at least a first local chunk and a second local chunk, rearrange an order of the first local chunk and the second local chunk to yield a locally interleaved data set, and write the locally interleaved data set to a first row of a first memory; wherein the locally interleaved data set includes at least a first global chunk stored to a first column of the first memory, and a second global chunk stored to a second column of the first memory; and a column controlled interleaver circuit operable to: access the locally interleaved data set from the first row of the first memory, store the first global chunk to the first column and a second row of a second memory, store the second global chunk to the second column and a third row of the second memory.
A data processing system shuffles data efficiently. It includes a local interleaver circuit that receives a data input containing at least two local chunks, rearranges the order of these chunks, and writes the rearranged data (locally interleaved data set) into a first row of a first memory. This locally interleaved data set has at least two global chunks that are stored in the first and second columns of the first memory. A column-controlled interleaver circuit then reads the data from the first row of the first memory and stores the first global chunk into the first column and a second row of a second memory, and the second global chunk into the second column and a third row of the second memory.
2. The data processing circuit of claim 1 , wherein the data processing system is implemented as part of a device selected from a group consisting of: a storage device and a receiving device.
The data processing system, as described above, is part of either a storage device (like a hard drive or SSD) or a receiving device (like a network receiver). The system efficiently shuffles data by rearranging local data chunks into a locally interleaved dataset, storing global chunks of this set into columns of a first memory, and then transferring those global chunks to columns of a second memory.
3. The data processing system of claim 1 , wherein the data processing system is implemented as part of an integrated circuit.
The data processing system, as described above, is implemented within an integrated circuit (IC), meaning it's a hardware component on a chip. The system efficiently shuffles data by rearranging local data chunks into a locally interleaved dataset, storing global chunks of this set into columns of a first memory, and then transferring those global chunks to columns of a second memory.
4. The data processing system of claim 1 , wherein the first row of the first memory is randomly selected.
The data processing system, as described above, writes the locally interleaved data set to a randomly selected first row of the first memory. The system efficiently shuffles data by rearranging local data chunks into a locally interleaved dataset, storing global chunks of this set into columns of a first memory, and then transferring those global chunks to columns of a second memory. Using a random row adds to the shuffle.
5. The data processing system of claim 1 , wherein the second row of the second memory is randomly selected, and wherein the third row of the second memory is randomly selected.
The data processing system, as described above, stores global data chunks into the second memory using randomly selected rows. Specifically, the second row (for the first global chunk) and the third row (for the second global chunk) of the second memory are chosen randomly. The system shuffles data by rearranging local data chunks into a locally interleaved dataset, storing global chunks of this set into columns of a first memory, and then transferring those global chunks to columns of a second memory. The use of random row selection enhances the data shuffling process.
6. The data processing system of claim 1 , wherein the first column of the second memory is selected to correspond to the first column of the first memory, and wherein the second column of the second memory is selected to correspond to the second column of the first memory.
In the data processing system described above, when the global data chunks are moved from the first memory to the second memory, the columns are aligned. The first global chunk that was stored in the first column of the first memory is stored in the first column of the second memory. Similarly, the second global chunk from the second column of the first memory goes to the second column of the second memory. The system shuffles data by rearranging local data chunks into a locally interleaved dataset, storing global chunks of this set into columns of a first memory, and then transferring those global chunks to columns of a second memory.
7. The data processing system of claim 1 , wherein the system further comprises: a data detector circuit operable to apply a data detection algorithm to a data set to yield the data input; and a data decoder circuit operable to apply a data decode algorithm to a globally interleaved data set generated by accessing the second row of the second memory including the first global chunk.
The data processing system from above also includes a data detector and a data decoder. The data detector applies a data detection algorithm to a data set to produce the data input that gets shuffled. The data decoder applies a data decode algorithm to the globally interleaved data set, which is accessed from the second row of the second memory and includes the first global chunk. The shuffling process involves rearranging local chunks, storing global chunks into memory columns, and transferring them between memory locations for efficient processing.
8. The data processing circuit of claim 7 , wherein the data detection algorithm is selected from a group consisting of: a maximum a posteriori data detection algorithm, and a Viterbi algorithm data detection algorithm.
The data processing system from the previous description includes a data detector and a data decoder, where the data detection algorithm can be either a maximum a posteriori (MAP) algorithm or a Viterbi algorithm. The data detector processes a dataset to yield a data input that is then shuffled. The system shuffles data by rearranging local data chunks into a locally interleaved dataset, storing global chunks of this set into memory columns, and transferring them between memory locations before decoding.
9. The data processing circuit of claim 7 , wherein the data decode algorithm is a low density parity check algorithm.
The data processing system from a prior description includes a data detector and a data decoder, where the data decode algorithm is a low-density parity-check (LDPC) algorithm. The system shuffles data by rearranging local data chunks into a locally interleaved dataset, storing global chunks of this set into memory columns, and transferring them between memory locations. The LDPC algorithm is used to decode the globally interleaved data, improving error correction.
10. A storage device, the storage device comprising: a storage medium; a head assembly disposed in relation to the storage medium and operable to provide a sensed signal corresponding to information on the storage medium; a read channel circuit including: an analog to digital converter circuit operable to sample an analog signal derived from the sensed signal to yield a series of digital samples; an equalizer circuit operable to equalize the digital samples to yield an equalized output; a data detector circuit operable to apply a data detection algorithm to the equalized output to yield a detected output; a local interleaver circuit operable to: receive a data input that includes at least a first local chunk and a second local chunk, rearrange an order of the first local chunk and the second local chunk to yield a locally interleaved data set, and write the locally interleaved data set to a first row of a first memory; wherein the locally interleaved data set includes at least a first global chunk stored to a first column of the first memory, and a second global chunk stored to a second column of the first memory; a column controlled interleaver circuit operable to: access the locally interleaved data set from the first row of the first memory, store the first global chunk to the first column and a second row of a second memory, store the second global chunk to the second column and a third row of the second memory; wherein the first column of the second memory corresponds to the first column of the first memory, and wherein the second column of the second memory corresponds to the second column of the first memory; and a data decoder circuit operable to apply a data decode algorithm to a globally interleaved data set generated by accessing the second row of the second memory including the first global chunk.
A storage device includes a storage medium, a read head, and a read channel circuit. The read channel circuit has an analog-to-digital converter (ADC) that samples the signal from the read head, an equalizer that refines the digital samples, a data detector that applies a data detection algorithm to create a detected output, and a local interleaver. The local interleaver rearranges data chunks and writes them to the first memory. A column-controlled interleaver then shuffles data between the first and second memories, aligning columns to transfer global chunks. A data decoder then applies a data decode algorithm to the globally interleaved data. The first column of the second memory corresponds to the first column of the first memory, and the second column of the second memory corresponds to the second column of the first memory.
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September 30, 2014
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