Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method of synthesizing a circuit design comprising: receiving a high level description of a circuit design into an electronic design automation system; receiving a user specification into the electronic design automation system, the user specification selecting a reliability circuit feature to add to the circuit design; adding the reliability circuit feature to the high level description of the circuit design based upon the user specification to generate a modified high level description of the circuit design; and producing a netlist of the circuit design with the reliability circuit feature in response to the modified high level description of the circuit design.
A method for automatically adding reliability features to a circuit design uses an electronic design automation (EDA) system. The system receives a high-level description of the circuit and a user-defined specification detailing which reliability feature to add. Based on this specification, the EDA tool modifies the circuit's high-level description to incorporate the reliability feature. Finally, the system outputs a netlist of the modified circuit, including the added reliability feature. The netlist describes the connections between different circuit components.
2. The method of claim 1 , wherein the high level description is code of a hardware description language describing the circuit design; the user specification is a data file; and the netlist maps and interconnects circuit cells of the circuit design to perform the function of the circuit design and the function of the added reliability circuit feature.
The method of claim 1 is further specified where the high-level description of the circuit design is code written in a hardware description language (HDL). The user specification providing the reliability feature is a data file. The output netlist includes mapping and interconnection details of the circuit cells. These cells are arranged to implement both the original circuit's function and the added reliability function.
3. The method of claim 1 , further comprising: identifying a list of elements of the circuit design; presenting the list of elements of the circuit design to a user; and receiving a user selection of the reliability circuit feature in response to the list of elements of the circuit design.
The method of claim 1 is further enhanced by first identifying elements of the circuit design. This list of elements is presented to the user. The user selects the specific reliability feature to apply based on this list of design elements. This allows for targeted application of reliability measures.
4. The method of claim 3 , wherein the list of elements of the circuit design include one or more of storage elements, computing elements and communication elements.
In the method of claim 3, the identified circuit elements presented to the user for selection include one or more of the following: storage elements (like memory cells), computing elements (like adders or multipliers), and communication elements (like buses or interfaces). This helps the user focus on critical areas for adding reliability features.
5. The method of claim 1 , wherein the user specification specifies the automatic application of a parity reliability circuit feature for at least one design element of the initial circuit design.
In the method of claim 1, the user specification automatically applies a parity reliability feature to at least one design element of the original circuit design. Parity checks are a simple form of error detection.
6. The method of claim 1 , wherein the user specification specifies the automatic application of an error correction code reliability circuit feature for at least one design element of the initial circuit design.
In the method of claim 1, the user specification automatically applies an error correction code (ECC) reliability feature to at least one design element of the initial circuit design. ECC allows for the detection and correction of errors.
7. The method of claim 1 , further comprising: adding detection logic to the initial circuit design to detect an illegal state and reset a state machine.
The method of claim 1 further includes adding detection logic to the original circuit design. This detection logic identifies illegal states and resets a state machine within the circuit. This increases reliability by preventing the circuit from getting stuck in invalid configurations.
8. The method of claim 7 , wherein the detection logic detects at least a single bit error.
In the method of claim 7, the added detection logic is capable of detecting at least a single-bit error. This error detection capability improves state machine robustness.
9. The method of claim 1 , further comprising: determining from a user specification that the added reliability circuit feature include at least one output pin for coupling to another integrated circuit.
The method of claim 1 further allows the added reliability feature to include at least one output pin intended for connection to another integrated circuit. The user specification indicates this requirement.
10. The method of claim 1 , wherein the circuit design includes a fault isolation register, the user specification specifies that the added reliability circuit feature include at least one output to couple to the fault isolation register, and the at least one output indicates fault or no-fault in an element of the circuit design.
In the method of claim 1, the circuit design contains a fault isolation register. The user specification dictates that the added reliability feature must include at least one output that connects to this fault isolation register. This output signals whether a fault is present or absent in an element of the circuit.
11. The method of claim 2 , wherein the modified input model is a modified high level description of the initial circuit design modified with the reliability circuit feature, and the producing of the output model includes receiving the modified high level description, mapping circuit cells of a cell library in a technology file into the netlist in response to the modified high level description, and storing the netlist into an integrated circuit design database.
In the method of claim 2 (where the high-level description is code in a hardware description language), the modified high-level description now includes the reliability feature. Producing the output netlist involves receiving this modified description, mapping circuit cells from a cell library (specified in a technology file) into the netlist based on the modified description, and storing the resulting netlist in an integrated circuit design database.
12. An electronic design automation system to synthesize a circuit design, comprising: a processor to execute instructions; a non-transitory processor readable medium including instructions stored therein for execution by the processor, including instructions to provide an input interface to receive a high level description of the circuit design and a user specification selecting a reliability circuit feature to add to the circuit design; instructions to add the reliability circuit feature to the high level description of the circuit design based upon the user specification; and instructions to provide an output interface to present a netlist of the circuit design with the reliability circuit feature.
An electronic design automation (EDA) system synthesizes a circuit design. The system includes a processor and a non-transitory memory storing instructions. These instructions, when executed, perform these actions: receiving a high-level description of the circuit and a user specification selecting a reliability feature to add; adding the reliability feature to the circuit's high-level description based on the user input; and outputting a netlist of the circuit that now includes the reliability feature.
13. The electronic design automation system of claim 12 , wherein: the user specification is a data file; and the netlist maps and interconnects circuit cells to perform the function of the circuit design and the function of the added reliability circuit feature.
The electronic design automation system of claim 12 is further defined as the user specification is a data file. The netlist maps and interconnects circuit cells in such a way to perform both the original circuit's functionality and the added reliability feature's function.
14. The electronic design automation system of claim 12 , further comprising: a display to present a list of identified design elements to a user to assist in selecting the reliability circuit feature.
The electronic design automation system of claim 12 includes a display. The display presents a list of identified design elements to the user, assisting in selecting an appropriate reliability feature.
15. The electronic design automation system of claim 12 , wherein: the circuit design includes a fault isolation register, the user specification specifies that the added reliability circuit feature include at least one output to couple to the fault isolation register, and the at least one output indicates fault or no-fault in an element of the circuit design.
In the electronic design automation system of claim 12, the circuit includes a fault isolation register. The user specification dictates that the added reliability feature must include at least one output to couple to the fault isolation register. That output indicates whether an element of the circuit has a fault or not.
16. A non-transitory computer readable medium storing a set of program instructions that, when executed by a processor, cause the processor to perform the operations of: receiving a high level description of a circuit design into an electronic design automation system; receiving a user specification into the electronic design automation system, the user specification selecting a reliability circuit feature to add to the circuit design; adding the reliability circuit feature to the high level description of the circuit design based upon the user specification; and producing a netlist of the circuit design with the reliability circuit feature.
A non-transitory computer-readable medium stores program instructions that, when executed by a processor, cause the processor to synthesize a circuit design. This involves: receiving a high-level description of the circuit and a user specification selecting a reliability circuit feature; adding the reliability feature to the circuit's high-level description based on the user input; and producing a netlist of the circuit design with the added reliability feature.
17. The non-transitory computer readable medium of claim 16 , wherein the user specification specifies the automatic application of a parity reliability circuit feature for at least one design element of the initial circuit design.
In the computer-readable medium of claim 16, the user specification automatically applies a parity reliability feature to at least one design element of the initial circuit design.
18. The non-transitory computer readable medium of claim 16 , wherein the user specification specifies the automatic application of an error correction code reliability circuit feature for at least one design element of the initial circuit design.
In the computer-readable medium of claim 16, the user specification automatically applies an error correction code (ECC) reliability feature for at least one design element of the initial circuit design.
19. The non-transitory computer readable medium of claim 16 , wherein the set of program instructions, when executed by the processor, cause the processor to further perform the operations of adding detection logic to the initial circuit design to detect an illegal state and reset a state machine.
The computer-readable medium of claim 16 further contains instructions to add detection logic to the original circuit design. This logic detects illegal states and resets a state machine.
20. The non-transitory computer readable medium of claim 16 , wherein the non-transitory computer readable medium is a computer readable storage media.
The non-transitory computer-readable medium as described in claim 16 is a computer-readable storage media.
21. The non-transitory computer readable medium of claim 16 , wherein the circuit design includes a fault isolation register, and the user specification specifies that the added reliability circuit feature include at least one output to couple to the fault isolation register.
In the computer-readable medium of claim 16, the circuit design includes a fault isolation register, and the user specification indicates that the added reliability feature must have at least one output that connects to the fault isolation register.
22. The non-transitory computer readable medium of claim 21 , wherein the at least one output indicates fault or no-fault in an element of the circuit design.
In the computer-readable medium of claim 21, the output connected to the fault isolation register indicates whether a fault is present or absent in an element of the circuit.
23. An integrated circuit comprising: on a monolithic substrate, a first synthesized circuit synthesized by a design system with a first added reliability circuit, the first added reliability circuit to detect and correct a circuit fault in the first synthesized circuit; a first output trace coupled to the first added reliability circuit, the first output trace 804 to indicate fault or no-fault in the first synthesized circuit; and a fault isolation register coupled to the first output trace, the fault isolation register 806 to register a circuit fault in the first synthesized circuit to enable selection of one or more redundant circuits to continue to process data.
An integrated circuit contains a first synthesized circuit that was created using a design system that added a reliability circuit. This reliability circuit is designed to detect and correct circuit faults in the first circuit. An output trace is connected to the reliability circuit, indicating the presence or absence of a fault in the first circuit. A fault isolation register is connected to the output trace, logging circuit faults in the first circuit. This allows for selection of redundant circuits to continue data processing.
24. The integrated circuit of claim 23 , wherein the first synthesized circuit is a state machine and the first added reliability circuit is an error detection circuit to detect one or more bit errors in the states of the state machine and reset the one or more bit errors to reset the state of the state machine.
In the integrated circuit of claim 23, the first synthesized circuit is a state machine. The added reliability circuit is an error detection circuit capable of detecting one or more bit errors in the state machine's states. When errors are detected, the circuit resets the state machine to a known good state.
25. The integrated circuit of claim 23 , wherein the first synthesized circuit is a state machine and the first added reliability circuit is an illegal state detection circuit to detect an illegal state of the state machine and reset the state machine.
In the integrated circuit of claim 23, the first synthesized circuit is a state machine, and the added reliability circuit is an illegal state detection circuit that detects an illegal state and resets the state machine.
26. An integrated circuit comprising: on a monolithic substrate, a first circuit synthesized by a design system with a first added reliability circuit, the first added reliability circuit to detect a fault in the first circuit; a first output trace coupled to the first added reliability circuit, the first output trace to indicate fault or no-fault in the first circuit; a second circuit synthesized by a design system with a second added reliability circuit, the second added reliability circuit to detect a fault in the second circuit; a second output trace coupled to the second added reliability circuit, the second output trace to indicate fault or no-fault in the second circuit; and a fault isolation register coupled to the first output trace and the second output trace, the fault isolation register to register a fault in one or both of the first circuit and the second circuit.
An integrated circuit includes a first circuit synthesized with a reliability circuit designed to detect faults. A first output trace indicates fault or no-fault in the first circuit. A second circuit is also synthesized with its own reliability circuit to detect faults, with a second output trace for fault indication. A fault isolation register connected to both output traces logs faults in either or both of the circuits.
27. The integrated circuit of claim 26 , wherein the second circuit is a redundant circuit for the first circuit, and the fault isolation register to enable between the first circuit and the second circuit in response to a detection of a fault in the second circuit or the first circuit, respectively, so that the integrated circuit may continue to process data.
In the integrated circuit of claim 26, the second circuit is a redundant backup for the first circuit. The fault isolation register facilitates switching between the first and second circuits in response to detecting a fault in either one. This allows the overall integrated circuit to continue data processing even when a component fails.
28. The integrated circuit of claim 26 , wherein the first added reliability circuit is an error correction encoder circuit to generate encoded data for transmission to the second circuit, and the second added reliability circuit is an error correction decoder circuit to detect and correct a fault in the received encoded data.
In the integrated circuit of claim 26, the first reliability circuit is an error correction encoder that generates encoded data for transmission to the second circuit. The second reliability circuit is an error correction decoder designed to detect and correct errors in the received encoded data.
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October 7, 2014
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