Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method of routing nets in an integrated circuit comprising: creating, by a computer, at least one robust output pin structure comprising multiple wire segments on one or more metal layers; using said multiple wire segments for routing to one or more receiving buffers of said nets; and adding wiring connections between output pin shapes of one or more driving buffers of said nets and said at least one robust output pin structure determined by requirements of electrical and reliability metrics, said robust output pin structure located between said one or more driving buffers and said one or more receiving buffers, wherein said at least one robust output pin structure is placed substantially adjacent to said output pin shapes of said one or more driving buffers for adding said wiring connections iteratively based on satisfying said electrical and reliability metrics.
A method for routing wires in an integrated circuit uses a computer to create a "robust output pin structure." This structure consists of multiple wire segments on one or more metal layers. These wire segments are used to route signals to receiving buffers of the circuit's nets. Wiring connections are added between the output pins of the driving buffers and this robust output pin structure. This structure is placed close to the driving buffers. The connections are added iteratively, with each iteration checking if electrical and reliability requirements (like signal delay and current limits) are met. This process optimizes the wiring for performance and reliability.
2. The method of claim 1 further comprising creating at least one robust input pin structure comprising said multiple wire segments on said one or more metal layers.
The wiring method described above also creates a "robust input pin structure," which like the output structure, uses multiple wire segments on one or more metal layers. This input structure is used in addition to the robust output pin structure comprising multiple wire segments on one or more metal layers for routing to one or more receiving buffers, and adding wiring connections between output pin shapes of one or more driving buffers of said nets and said at least one robust output pin structure determined by requirements of electrical and reliability metrics, said robust output pin structure located between said one or more driving buffers and said one or more receiving buffers, wherein said at least one robust output pin structure is placed substantially adjacent to said output pin shapes of said one or more driving buffers for adding said wiring connections iteratively based on satisfying said electrical and reliability metrics.
3. The method of claim 1 wherein said nets to be routed comprise high performance clock nets connecting one or more driving clock buffers to one or more receiving buffers.
In the wiring method described where a computer creates a "robust output pin structure" consisting of multiple wire segments on one or more metal layers to route signals to receiving buffers and wiring connections are added between the output pins of the driving buffers and the output pin structure placed close to the driving buffers with connections added iteratively checking electrical and reliability requirements, the nets being routed are high-performance clock nets. These clock nets connect the driving clock buffers to receiving buffers, ensuring precise timing signals throughout the circuit.
4. The method of claim 1 wherein said creating said routing based on electrical current is obtained from parameter extraction and simulation, or by way of model approximations.
In the wiring method described where a computer creates a "robust output pin structure" consisting of multiple wire segments on one or more metal layers to route signals to receiving buffers and wiring connections are added between the output pins of the driving buffers and the output pin structure placed close to the driving buffers with connections added iteratively checking electrical and reliability requirements, the electrical current values used for routing decisions are obtained through parameter extraction and simulation of the circuit layout, or by using model approximations to estimate these values.
5. The method of claim 1 further comprising defining a bounding box by a physical location of said output pin shapes of each of said driving buffers and receiving buffers and creating said robust pin structure on at least one metal layer in a physical location closest to a geometric center of said bounding box.
The wiring method described where a computer creates a "robust output pin structure" consisting of multiple wire segments on one or more metal layers to route signals to receiving buffers and wiring connections are added between the output pins of the driving buffers and the output pin structure placed close to the driving buffers with connections added iteratively checking electrical and reliability requirements, first defines a bounding box that encompasses the physical locations of the output pins of both the driving and receiving buffers. The robust pin structure is then created on at least one metal layer at a location closest to the geometric center of this bounding box.
6. The method of claim 1 wherein evaluating said electrical and reliability metrics are based on estimated capacitance loads wherein actual capacitances are still unknown.
In the wiring method described where a computer creates a "robust output pin structure" consisting of multiple wire segments on one or more metal layers to route signals to receiving buffers and wiring connections are added between the output pins of the driving buffers and the output pin structure placed close to the driving buffers with connections added iteratively checking electrical and reliability requirements, the evaluation of electrical and reliability metrics (like signal delay and current limits) is based on estimated capacitance loads. This means that the actual capacitance values are not yet known, and the routing is initially based on estimations.
7. The method of claim 1 wherein said electrical metrics comprise signal delay, signal slew, and signal skew.
In the wiring method described where a computer creates a "robust output pin structure" consisting of multiple wire segments on one or more metal layers to route signals to receiving buffers and wiring connections are added between the output pins of the driving buffers and the output pin structure placed close to the driving buffers with connections added iteratively checking electrical and reliability requirements, the electrical metrics that are evaluated include signal delay (how long it takes for a signal to propagate), signal slew (the rate of voltage change), and signal skew (the difference in arrival times of a signal at different points).
8. The method of claim 1 wherein said reliability metrics comprise reliability limits on electric currents.
In the wiring method described where a computer creates a "robust output pin structure" consisting of multiple wire segments on one or more metal layers to route signals to receiving buffers and wiring connections are added between the output pins of the driving buffers and the output pin structure placed close to the driving buffers with connections added iteratively checking electrical and reliability requirements, the reliability metrics that are evaluated comprise reliability limits on electric currents flowing through the wires. This ensures that the current levels do not exceed the maximum allowed values, preventing electromigration or other reliability issues.
9. The method of claim 6 further comprising iteratively repeating said electrical evaluation and said routing additional wiring connections until said electrical and reliability requirements are met.
Building on the wiring method where the evaluation of electrical and reliability metrics is based on estimated capacitance loads, the electrical evaluation and addition of wiring connections are repeated iteratively until the electrical and reliability requirements are met. This iterative process refines the routing based on updated electrical characteristics until the desired performance and reliability are achieved. A computer creates a "robust output pin structure" consisting of multiple wire segments on one or more metal layers to route signals to receiving buffers, and wiring connections are added between the output pins of the driving buffers and the output pin structure placed close to the driving buffers checking electrical and reliability requirements.
10. The method of claim 9 , wherein said iterative repeating electrical evaluation concludes when said electrical and reliability metrics change by less than a predetermined threshold.
In the iterative electrical evaluation process described where, the electrical evaluation and addition of wiring connections are repeated iteratively until the electrical and reliability requirements are met, the iterative process concludes when the electrical and reliability metrics change by less than a predetermined threshold. This threshold defines the acceptable level of variation and ensures that the routing converges to a stable solution. A computer creates a "robust output pin structure" consisting of multiple wire segments on one or more metal layers to route signals to receiving buffers, and wiring connections are added between the output pins of the driving buffers and the output pin structure placed close to the driving buffers checking electrical and reliability requirements based on estimated capacitance loads.
11. The method of claim 1 , wherein said routing said design routing nets is achieved when a single route or an available route are determined to be inadequate.
In the wiring method described where a computer creates a "robust output pin structure" consisting of multiple wire segments on one or more metal layers to route signals to receiving buffers and wiring connections are added between the output pins of the driving buffers and the output pin structure placed close to the driving buffers with connections added iteratively checking electrical and reliability requirements, the design nets are routed only when a single route or an available route is determined to be inadequate. The method is invoked when standard routing techniques fail to meet performance or reliability targets.
12. The method of claim 1 wherein at least two robust pin structures are created on opposed sides of said driving buffers and said output pin shapes of said driving buffers extend in opposite directions to be connected to said two or more robust pin structures.
In the wiring method described where a computer creates a "robust output pin structure" consisting of multiple wire segments on one or more metal layers to route signals to receiving buffers and wiring connections are added between the output pins of the driving buffers and the output pin structure placed close to the driving buffers with connections added iteratively checking electrical and reliability requirements, at least two robust pin structures are created on opposite sides of the driving buffers. The output pins of the driving buffers extend in opposite directions to connect to these two or more robust pin structures, creating a more balanced and reliable connection.
13. A method of routing nets in an integrated circuit comprising: defining, by a computer, a physical region around each driving buffer of said nets; creating a robust pin structure as a local mesh of wires on two or more metal layers in said physical region, said each driving buffer being located substantially adjacent to said created robust pin structure; connecting said local mesh of wires to output pin shapes of said driving buffers; using said local mesh of wires to route input pin shapes of one or more receiving buffers, said robust pin structure created between said each driving buffer and said one or more receiving buffers; and adding or subtracting wires from said local mesh of wires coupled between said robust pin structure and said each driving buffer iteratively to meet requirements of one or more electrical and reliability metrics associated with said nets.
A method for routing wires in an integrated circuit defines a physical region around each driving buffer. Within this region, a "robust pin structure" is created as a local mesh of wires on two or more metal layers. Each driving buffer is placed close to this robust pin structure. The local mesh of wires is connected to the output pins of the driving buffers and is then used to route signals to the input pins of one or more receiving buffers. The robust pin structure is positioned between each driving buffer and the receiving buffers. Wires are added to or subtracted from the local mesh iteratively to meet electrical and reliability requirements.
14. The method of claim 13 wherein said routed nets are high performance clock nets connected to one or more driving clock buffers to one or more of said receiving buffers.
In the wiring method using a "robust pin structure" as a local mesh of wires on two or more metal layers in a physical region around each driving buffer where the mesh connects to output pins and is used to route signals to receiving buffers and wires are added/subtracted iteratively to meet electrical and reliability requirements, the routed nets are high-performance clock nets connecting one or more driving clock buffers to one or more receiving buffers.
15. The method of claim 13 wherein said local mesh is based on an estimated capacitive load.
In the wiring method using a "robust pin structure" as a local mesh of wires on two or more metal layers in a physical region around each driving buffer where the mesh connects to output pins and is used to route signals to receiving buffers and wires are added/subtracted iteratively to meet electrical and reliability requirements, the local mesh structure is based on an estimated capacitive load.
16. The method of claim 13 further comprising iteratively repeating an electrical evaluation and increasing wire density in said local mesh until said electrical and reliability requirements are met.
The wiring method using a "robust pin structure" as a local mesh of wires on two or more metal layers in a physical region around each driving buffer where the mesh connects to output pins and is used to route signals to receiving buffers and wires are added/subtracted iteratively to meet electrical and reliability requirements further includes iteratively repeating an electrical evaluation and increasing wire density in the local mesh until the electrical and reliability requirements are met.
17. The method of claim 16 , wherein said iterative electrical evaluation is completed when said electrical and reliability metrics change by less than a predetermined threshold.
In the iterative process of electrical evaluation and increasing wire density until electrical and reliability requirements are met in the wiring method using a "robust pin structure" as a local mesh of wires on two or more metal layers in a physical region around each driving buffer where the mesh connects to output pins and is used to route signals to receiving buffers and wires are added/subtracted iteratively to meet electrical and reliability requirements, the evaluation is completed when the electrical and reliability metrics change by less than a predetermined threshold.
18. The method of claim 16 further comprising creating a model consisting of circuit parameters for relevant metal wires and circuit parameters for driving buffers and receiving buffers including reliability limits on buffer current and buffer power.
The wiring method using a "robust pin structure" as a local mesh of wires on two or more metal layers in a physical region around each driving buffer where the mesh connects to output pins and is used to route signals to receiving buffers and wires are added/subtracted iteratively to meet electrical and reliability requirements including iteratively repeating an electrical evaluation and increasing wire density until electrical and reliability requirements are met, further creates a model consisting of circuit parameters for the metal wires, driving buffers, and receiving buffers including reliability limits on buffer current and buffer power.
19. The method of claim 17 wherein said electrical and reliability metrics comprise electrical currents through said wire segments, effective resistance and delay of said wiring segments, computed using electrical simulation or model approximation.
In the wiring method using a "robust pin structure" as a local mesh of wires on two or more metal layers in a physical region around each driving buffer where the mesh connects to output pins and is used to route signals to receiving buffers and wires are added/subtracted iteratively to meet electrical and reliability requirements including iteratively repeating an electrical evaluation and increasing wire density until electrical and reliability requirements are met, the electrical and reliability metrics comprise electrical currents through the wire segments, effective resistance and delay of the wiring segments, computed using electrical simulation or model approximation. The evaluation is completed when the electrical and reliability metrics change by less than a predetermined threshold.
20. A non-transitory storage medium for storing a wiring-optimal routing solution for high performance clock nets in an integrated circuit, readable by a processing circuit storing instructions for executing by the processing circuit for performing a method comprising: creating at least one robust output pin structure comprising multiple wire segments on one or more metal layers; using said wire segments for routing to one or more receiving buffers of said nets; and adding wiring connections between output pin shapes of one or more driving buffers of said nets and said at least one robust output pin structure determined by requirements of electrical and reliability metrics, said robust output pin structure located between said one or more driving buffers and said one or more receiving buffers, wherein said at least one robust output pin structure is placed substantially adjacent to said output pin shapes of said one or more driving buffers for adding said wiring connections iteratively based on satisfying said electrical and reliability metrics.
A non-transitory storage medium stores instructions for routing high-performance clock nets in an integrated circuit. The instructions, when executed, perform the following method: creating at least one robust output pin structure comprising multiple wire segments on one or more metal layers; using these wire segments for routing to one or more receiving buffers; and adding wiring connections between output pins of one or more driving buffers and the robust output pin structure based on electrical and reliability metrics. The robust output pin structure is located between the driving and receiving buffers and is placed close to the output pins of the driving buffers. Wiring connections are added iteratively until the electrical and reliability metrics are satisfied.
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October 14, 2014
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