Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor apparatus comprising: a first semiconductor device; a second semiconductor device having a larger load capacitance than the first semiconductor device; and a signal transmission path to connect the first semiconductor device and the second semiconductor device, wherein the signal transmission path includes a first wiring on a side of the first semiconductor device, a second wiring on a side of the second semiconductor device and a resistor between the first wiring and the second wiring, an impedance of the second wiring on the side of the second semiconductor device having the large load capacitance is larger than an impedance of the first wiring on the side of the first semiconductor device having the small load capacitance, and a length of the second wiring is longer than a length of the first wiring.
A semiconductor apparatus improves signal transmission between a first semiconductor device (like a memory controller) and a second semiconductor device (like a memory device) which has a larger load capacitance. A signal transmission path connects them, consisting of a first wiring on the first device's side, a second wiring on the second device's side, and a resistor in between. The second wiring (connected to the larger load capacitance) has a higher impedance and is longer than the first wiring (connected to the smaller load capacitance). This configuration helps manage signal reflections and improve signal speed.
2. The semiconductor apparatus according to claim 1 , wherein a signal transmitted from the first semiconductor device to the second semiconductor device is subjected to pre-emphasis.
The semiconductor apparatus from the previous description, which improves signal transmission between devices with different load capacitances using a resistor-divided wiring setup, also employs pre-emphasis. Specifically, when a signal is sent from the first semiconductor device (smaller load capacitance side) to the second semiconductor device (larger load capacitance side), the signal is pre-emphasized to compensate for signal degradation caused by the larger load capacitance. This sharpens the signal's rising edge.
3. The semiconductor apparatus according to claim 2 , wherein a signal transmitted from the second semiconductor device to the first semiconductor device is not subjected to pre-emphasis or is slightly subjected to pre-emphasis.
The semiconductor apparatus described earlier, which uses impedance-matched wiring with a resistor and pre-emphasis for signals going to the larger load, handles signals going the other direction differently. When a signal is transmitted from the second semiconductor device (larger load capacitance side) to the first semiconductor device (smaller load capacitance side), pre-emphasis is either not used or only slightly applied. This prevents excessive ringing in the signal due to reflections on the smaller load capacitance side.
4. The semiconductor apparatus according to claim 1 , wherein the impedance of the first wiring is smaller then a sum of a resistance value of the resistor and the impedance of the second wiring, and the impedance of the second wiring is substantially equal to a sum of the resistance value of the resistor and the impedance of the first wiring.
Focusing on the impedance matching within the semiconductor apparatus, the impedance of the first wiring (connected to the smaller load capacitance) is smaller than the sum of the resistor's resistance and the impedance of the second wiring (connected to the larger load capacitance). Conversely, the impedance of the second wiring is approximately equal to the sum of the resistor's resistance and the impedance of the first wiring. This configuration is designed to minimize signal reflections and optimize signal integrity.
6. The semiconductor apparatus according to claim 1 , wherein the second semiconductor device is a memory device, and the first semiconductor device is a memory controller to control the memory.
In a specific application of the semiconductor apparatus with optimized wiring, the second semiconductor device (having the larger load capacitance) is a memory device, such as RAM or flash memory. The first semiconductor device (having the smaller load capacitance) is a memory controller, responsible for managing and controlling the memory device. This configuration optimizes data transfer between the memory controller and memory.
7. The semiconductor apparatus according to claim 6 , wherein the memory device is a flash memory.
In the semiconductor apparatus where a memory controller communicates with a memory device, the memory device, which has the larger load capacitance, can be a flash memory. The flash memory stores data and is controlled by the memory controller, using the previously described wiring configuration to improve data transmission.
8. The semiconductor apparatus according to claim 1 , wherein the resistor is a resistance device or a collective resistance device.
The resistor used in the signal transmission path between the first and second semiconductor devices can be a discrete resistance device (single resistor) or a collective resistance device (resistor network). The resistor serves to balance the impedance and reduce signal reflections.
9. The semiconductor apparatus according to claim 1 , wherein the resistor is a resistor provided in a switching device or a connector.
The resistor used in the signal transmission path, besides being a standalone component, can also be integrated within a switching device (like a transistor) or a connector. The resistor still functions to balance impedance and manage signal reflections.
10. The semiconductor apparatus according to claim 1 , wherein the resistor is a resistor provided in a board.
The resistor used in the signal transmission path can also be implemented as a resistor that is placed directly on the circuit board itself, rather than as a discrete component. It still serves its function of impedance matching.
11. The semiconductor apparatus according to claim 1 , wherein a plurality of the signal transmission paths are provided to form a differential signal transmission path.
Instead of a single signal transmission path, the semiconductor apparatus can employ multiple such paths to create a differential signal transmission path. Using differential signaling improves noise immunity and overall signal integrity during data transmission.
12. The semiconductor apparatus according to claim 1 , further comprising a termination resistor on the side of the second semiconductor device relative to the second wiring.
In addition to the resistor between the first and second wiring segments, the semiconductor apparatus includes a termination resistor placed on the side of the second semiconductor device (the one with the larger load capacitance), positioned after the second wiring segment. This termination resistor further reduces signal reflections.
13. The semiconductor apparatus according to claim 1 , wherein a plurality of the second semiconductor devices are provided, the load capacitance of the second semiconductor device is a sum of load capacitances of the plurality of the second semiconductor devices, and the sum of the load capacitances is larger than the load capacitance of the first semiconductor device.
The semiconductor apparatus can be configured with multiple second semiconductor devices (each with a larger load capacitance). The total load capacitance is the sum of the capacitances of all the second devices. This total capacitance is greater than the load capacitance of the single first semiconductor device. The signal transmission system manages the combined load.
14. A signal transmission system comprising: a semiconductor device connection part connected to a semiconductor device as a memory controller; a memory device connection part connected to a memory device; and a signal transmission path to connect the semiconductor device connection part and the memory device connection part, wherein the signal transmission path includes a first wiring on a side of the semiconductor device connection part, a second wiring on a side of the memory device connection side and a resistor between the first wiring and the second wiring, an impedance of the second wiring on the side of the memory device connection part is larger than an impedance of the first wiring on the side of the semiconductor device connection part, and a length of the second wiring is longer than a length of the first wiring.
A signal transmission system connects a memory controller (via a semiconductor device connection part) to a memory device (via a memory device connection part). A signal transmission path connects them, including a first wiring on the memory controller side, a second wiring on the memory device side, and a resistor between them. The second wiring has a higher impedance and is longer than the first wiring.
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October 21, 2014
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