Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method for use in a system comprising a serial interconnection of first to N-th memory devices connected in-series and a memory controller configured to communicate with the interconnection, N being an integer greater than one, each of the N memory devices including a memory for storing data and being associated with a device identification, each of the N memory devices being selectable based on the device identification, each of the N memory devices being configured to transfer an enable signal received at its enable input to a successive memory device of the serial interconnection, each of the N memory devices being configured to transfer a command signal received at its signal input to the successive memory device based on device selection determination and in response to the enable signal received at its enable input, each of the N memory devices being configured to receive a clock signal at its clock input and to perform operations in response to the received clock signal, the method comprising: at the memory controller sending a command signal to the first memory device; the command signal including a device address identification for device selection, an operation instruction and a memory address identification; wherein, the device address identification, the operation instruction and the memory address identification form a modular command structure, the modular command structure being a byte basis, at an i-th memory device of the serial interconnection, i being 1≦i≦N receiving the command signal sent by the memory controller or transferred from a previous memory device, the receiving the command signal being enabled by the enable signal received at the enable input of the i-th memory device, determining whether the i-th memory device is selected based on the device address identification included in the received command signal and the associated device identification, in a case of determination where the i-th memory device is selected, providing a selection determination for processing, and in response to the selection determination for processing, processing the operation instruction included in the received command signal to access the memory included in the i-th memory device in accordance with the memory address identification included in the received command signal, in a case of determination where the i-th memory device is not selected, forwarding the received command signal including the device address identification, the operation instruction and the memory address identification formed in a modular command structure to the signal input of the successive memory device.
A memory system has a memory controller connected to multiple memory devices in series. Each memory device has its own unique ID and contains memory to store data. The memory controller sends a command to the first memory device, containing a device ID, an operation instruction (like read or write), and a memory address. Each memory device checks if the device ID in the command matches its own ID. If it matches, the device performs the operation at the specified address. If not, it passes the command to the next memory device in the series. The commands are structured in byte-sized modules for easy parsing.
2. The method of claim 1 , wherein the operation instruction represented by an operation code.
The method for memory access in a serial memory system as described in Claim 1 wherein the operation instruction that the memory controller sends (specifying read or write) is represented by a specific operation code (opcode). This opcode is part of the modular command structure sent to the memory devices, allowing them to identify the desired action.
3. The method of claim 1 , wherein the operation instruction comprises a data write instruction.
The method for memory access in a serial memory system as described in Claim 1, focuses on the case where the operation instruction sent by the memory controller to the memory devices is a "data write" instruction. This indicates that the controller wants to write data into a specific memory location within one of the memory devices.
4. The method of claim 3 , wherein at the memory controller, sending the command signal including the device address identification for device selection, the data write instruction, the memory address identification, data to be written, wherein, the device address identification, the data write instruction, the memory address identification and the data form a modular command structure.
The method for writing data to memory as described in Claim 3 expands on the command structure. When the memory controller sends a data write instruction, the command includes the device ID, the write instruction itself, the memory address where the data should be written, and the actual data to be written. All these components are arranged in a modular command structure for efficient transmission.
5. The method of claim 4 , wherein at the i-th memory device, the processing the operation instruction comprises: in response to the selection determination for processing, processing the data write instruction to write the data included in the received command signal, the data being written in the memory in accordance with the memory address identification included in the received command signal.
In the method of Claim 4, when a memory device receives a data write instruction and determines that it is the target device based on its device ID, it executes the write operation. This involves taking the data included in the command and writing it to the memory location specified by the memory address, as directed by the data write instruction.
6. The method of claim 1 , wherein the operation instruction comprises a data read instruction.
The method for memory access in a serial memory system as described in Claim 1, focuses on the case where the operation instruction sent by the memory controller to the memory devices is a "data read" instruction. This indicates that the controller wants to read data from a specific memory location within one of the memory devices.
7. The method of claim 6 , wherein at the memory controller, sending the command signal including the device address identification for device selection, the data read instruction and the memory address identification, wherein, the device address identification, the data read instruction and the memory address identification form a modular command structure.
The method for reading data from memory as described in Claim 6 expands on the command structure. When the memory controller sends a data read instruction, the command includes the device ID, the read instruction itself, and the memory address from where the data should be read. All these components are arranged in a modular command structure for efficient transmission.
8. The method of claim 7 , wherein at the i-th memory device, the processing the operation instruction comprises: in response to the selection determination for processing, processing the data read instruction included in the received command signal, the data stored in the memory being read out from the memory in accordance with the memory address identification included in the received command signal.
In the method of Claim 7, when a memory device receives a data read instruction and determines that it is the target device based on its device ID, it executes the read operation. This involves reading the data stored at the memory location specified by the memory address, as directed by the data read instruction, and making the data available to the memory controller.
9. The method of claim 1 , wherein at the i-th memory device, the determining whether the i-th memory device is selected comprises: comparing the device address identification of the command signal to the device address associated with the i-th memory device.
The method for device selection in a serial memory system as described in Claim 1 details how each memory device determines if it's the intended target of a command. The device compares the device ID included in the received command signal with its own pre-assigned device ID. This comparison is the basis for determining whether the device should process the command or forward it.
10. The method of claim 9 , wherein the comparing comprises: determining whether the device address identification of the command signal matches the device address associated with the i-th memory device to provide a determination result.
The comparison process described in Claim 9 involves determining whether the device ID in the command signal exactly matches the device ID associated with the specific memory device. This comparison results in a boolean "match" or "no match" determination that drives subsequent actions.
11. The method of claim 10 , wherein the determination result is provided as the selection determination for processing, when: the device address identification of the command signal is identical to the device address associated with the i-th memory device.
Building upon Claim 10, the "selection determination for processing" – the signal that tells a device whether to act on a command – is generated *only* when the device ID in the command signal is *identical* to the device's own address. A non-identical address results in forwarding the command to the next device.
12. A method for use in a system comprising a serial interconnection of first to N-th memory devices connected in-series and a memory controller configured to communicate with the interconnection, N being an integer greater than one, each of the N memory devices including a memory for storing data and being associated with a device identification, each of the N memory devices being selectable based on the device identification, each of the N memory devices being configured to transfer an enable signal received at its enable input to a successive memory device of the serial interconnection, each of the N memory devices being configured to transfer a command signal received at its signal input to the successive memory device based on device selection determination and in response to the enable signal received at its enable input, each of the N memory devices being configured to receive a clock signal at its clock input and to perform operations in response to the received clock signal, the method comprising: at the memory controller sending a first command signal to the first memory device; the first command signal including a first device address identification for device selection, a data write instruction, a memory address identification and data to be written, wherein, the first device address identification, the data write instruction, the memory address identification and the data form a modular command structure, at an i-th memory device of the serial interconnection, i being 1≦i≦N receiving the first command signal sent by the memory controller or propagated from a previous memory device, the receiving the first command signal being enabled by the enable signal received at the enable input of the i-th memory device, determining whether the i-th memory device is selected based on the first device address identification included in the received first command signal and the associated device identification, in a case of determination where the i-th memory device is selected, providing a selection determination for processing, and in response to the selection determination for processing, processing the data write instruction included in the received first command signal, the data included in the received first command signal being written in the memory included in the i-th memory device in accordance with the memory address identification included in the received first command signal, in a case of determination where the i-th memory device is not selected, forwarding the received first command signal including the first device address identification, the data write instruction, the memory address identification and the data formed in a modular command structure to the signal input of the successive memory device, at the memory controller sending a second command signal to the first memory device; the second command signal including a second the device address identification for device selection, a data read instruction and the memory address identification, wherein, the second device address identification, the data read instruction and the memory address identification form a modular command structure, at a j-th memory device of the serial interconnection, j being 1≦j≦N receiving the second command signal sent by the memory controller or propagated from a previous memory device, the receiving the second command signal being enabled by the enable signal received at the enable input of the j-th memory device, determining whether the j-th memory device is selected based on the second device address identification included in the received second command signal and the associated device identification, in a case of determination where the j-th memory device is selected, providing a selection determination for processing, and in response to the selection determination for processing, processing the data read instruction included in the received second command signal, the data previously written in the memory included in the j-th memory device in accordance with the memory address identification included in the received second command signal, in a case of determination where the j-th memory device is not selected, forwarding the received second command signal including the second device address identification, the data read instruction and the memory address identification formed in a modular command structure to the signal input of the successive memory device.
A memory system uses a serial chain of memory devices. A memory controller sends commands containing a device ID, instruction (read/write), and address. The first command writes data to a specific memory device. The target device is selected by matching the device ID in the command. The controller then sends a second command to read the data back. This second command also contains a device ID, instruction, and address to select the right memory device to read from. Data is written and read via modular command structures.
13. The method of claim 12 , wherein: at the memory controller, the sending the first command signal is performed before the sending the second command signal.
In the serial memory system described in Claim 12, the process of writing data to a memory device (sending the first command signal) always occurs *before* reading data from the same or a different device (sending the second command signal). This ensures that the data is available when the read operation is initiated.
14. The method of claim 13 , wherein: after the sending the first command signal to the first memory device by the memory controller, the i-th memory device performs the receiving the first command signal and the determining whether the i-th memory device is selected.
In the serial memory system as described in Claim 13, once the memory controller sends the first "write" command, the individual memory devices immediately start listening for the command, and determine if they've been selected before any other action is taken. This ensures timely selection and data storage.
15. The method of claim 14 , wherein: at the memory controller, after sending the first command signal, the sending the second command signal is performed.
As described in Claim 14, in the serial memory system, the sending of the *second* command signal, containing instructions for reading, is only started *after* the first "write" command signal has been sent to the serial chain. This means that writing happens before the corresponding read.
16. The method of claim 15 , wherein: after the sending the second command signal to the first memory device by the memory controller, the j-th memory device performs the receiving the second command signal and the determining whether the j-th memory device is selected.
Following up on Claim 15, after the memory controller transmits the second command signal, the individual memory devices start checking whether they are the target for the read operation. They compare the device identification included in the command with their own IDs.
17. A method for use in a system comprising a serial interconnection of first to N-th memory devices connected in-series and a memory controller configured to communicate with the interconnection, the memory controller including a storage element for storing data, N being an integer greater than one, each of the N memory devices including a temporary store element for temporarily storing data and being associated with a device identification, each of the N memory devices being selectable based on the device identification, each of the N memory devices being configured to transfer an enable signal received at its enable input to a successive memory device of the serial interconnection, each of the N memory devices being configure to transfer a command received at its signal input to the successive memory device based on device selection determination and in response to the enable signal received at its enable input, each of the N memory devices being configured to receive a clock signal at its clock input and to perform operations in response to the received clock signal, the method comprising: at the memory controller sending a first command signal to the first memory device; the first command signal including a first device address identification for device selection, an operation instruction for data storing and first data read from the storage element included in the memory controller, wherein, the first device address identification, the operation instruction and the first data form a modular command structure, at an i-th memory device of the serial interconnection, i being 1≦i≦N receiving the first command signal sent by the memory controller or propagated from a previous memory device, the receiving the first command signal being enabled by the enable signal received at the enable input of the i-th memory device, determining whether the i-th memory device is selected based on the first device address identification included in the received first command signal and the associated device identification, in a case of determination where the i-th memory device is selected, providing a selection determination for data storing, and in response to the selection determination for data storing, storing the first data included in the received first command signal in the temporary store element included in the selected i-th memory device; in a case of determination where the i-th memory device is not selected, forwarding the received first command signal including the first device address identification, the operation instruction and the first data formed in a modular command structure to the signal input of the successive memory device.
A memory system comprises a memory controller with its own data storage, and several memory devices linked serially. Each memory device includes a temporary storage element and is selectable via a unique ID. The memory controller reads data from its storage and sends it within a command to a specific memory device. The command includes the device ID, an operation instruction for data storage, and the actual data. The targeted memory device, identified by the device ID, then stores the received data in its temporary storage element. The whole structure is based around modular commands.
18. The method of claim 17 , wherein after sending the first command signal, at the memory controller sending a second command signal to the first memory device; the second command signal including a second device address identification for device selection, the an operation instruction for data storing and second data read from the storage element included in the memory controller, wherein, the second device address identification, the operation instruction and the second data form a modular command structure, at an j-th memory device of the serial interconnection, j being 145N receiving the second command signal sent by the memory controller or propagated from a previous memory device, the receiving the second command signal being enabled by the enable signal received at the enable input of the j-th memory device, determining whether the j-th memory device is selected based on the second device address identification included in the received second command signal and the associated device identification, in a case of determination where the j-th memory device is selected, providing a selection determination for data storing, and in response to the selection determination for data storing, storing the second data included in the received second command signal in the temporary store element included in the selected j-th memory device; in a case of determination where the j-th memory device is not selected, forwarding the received second command signal including the second device address identification, the operation instruction and the second data formed in a modular command structure to the signal input of the successive memory device.
Expanding on Claim 17, the memory controller sends a *second* command containing new data to *another* memory device (or possibly the same). This command also includes a device ID, an operation instruction for data storage, and the new data. This new memory device stores this second piece of data in its temporary storage.
19. The method of claim 18 , wherein after sending the second command signal, at the memory controller reading back the first and second data stored in the temporary store elements included in the i-th and j-th memory devices.
As described in Claim 18, after sending the second command and storing data in (potentially) two separate memory devices, the memory controller reads back the first and second data from the temporary storage locations in those devices. This retrieves the data that was previously offloaded.
20. The method of claim 19 , wherein after sending the second command signal, at the memory controller freeing up space in the storage element storing the first and second data.
In the system of Claim 19, following the transmission of the second command, the memory controller deallocates the memory space that was occupied by the first and second data in the controller's local storage. This makes room for new data.
21. The method of claim 20 , wherein after the freeing up space in the storage element, at the memory controller reading back the first and second data stored in the temporary store elements included in the i-th and j-th memory devices, the read backed first and second data being re-stored in the storage element of the memory controller.
Expanding on the memory management strategy of Claim 20, after freeing up storage in the memory controller, the first and second data, which were temporarily stored in the memory devices, are read back and then *re-stored* in the memory controller's storage element. This allows for continued operation of the memory controller, even after the data was temporarily displaced to the external devices.
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November 4, 2014
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