Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An integrated circuit (IC) device comprising: a shielding mesh having at least a first portion disposed in a first layer of said IC and at least a second portion disposed in said first layer and a second layer, wherein said shielding mesh comprises a first single layer shielding mesh and a first double layer shielding mesh which is coupled to said first single layer shielding mesh; at least a first signal line having a first unshielded portion, which is disposed in a first region of said IC which is adjacent to said first single layer shielding mesh, and having a first shielded portion which is disposed in said first single layer shielding mesh, and having a second shielded portion which is disposed in said first double layer shielding mesh.
An integrated circuit (IC) has a shielding mesh with single and double layer portions. The single-layer portion is in one layer of the IC, while the double-layer portion spans two layers and is connected to the single-layer mesh. A signal line runs through the IC, having an unshielded segment near the single-layer mesh, a shielded segment within the single-layer mesh, and another shielded segment within the double-layer mesh. This arrangement provides partial shielding of the signal line from interference.
2. The IC as in claim 1 wherein said first signal line also comprises a third shielded portion which is disposed in a second single layer shielding mesh and a second unshielded portion which is disposed in a second region of said IC which is adjacent to said second single layer shielding mesh.
In addition to the features described in the previous IC shielding arrangement, the signal line also includes a third shielded segment that resides within a second single-layer shielding mesh and a second unshielded portion located adjacent to this second single-layer shielding mesh. This adds another layer of shielding to the signal line in a different region of the IC.
3. The IC as in claim 2 wherein said shielding mesh comprises a second double layer shielding mesh which is coupled to said second single layer shielding mesh and wherein said first signal line comprises a fourth shielded portion which is disposed in said second double layer shielded mesh.
Building upon the previous IC shielding design, the shielding mesh includes a second double-layer shielding mesh that is connected to the second single-layer shielding mesh. Furthermore, the signal line has a fourth shielded segment located within this second double-layer shielding mesh, further increasing the overall shielding of the signal.
4. The IC as in claim 2 wherein each of said first single layer shielding mesh, said first double layer shielding mesh, and said second single layer shielding mesh comprises a first plurality of reference voltage lines designed to provide a first reference voltage and a second plurality of reference voltage lines designed to provide a second reference voltage.
Expanding upon the IC shielding design where a signal line is shielded by single and double layer meshes, these meshes - first single layer, first double layer, and second single layer - consist of alternating lines carrying two different reference voltages (e.g., ground and power). This reference voltage line arrangement provides a more effective shielding structure by reducing noise coupling.
5. The IC as in claim 4 , further comprising: at least one reference voltage line, designed to provide said first reference voltage, disposed between a pair of adjacent second plurality of reference voltage lines in said shielding mesh, wherein said at least one reference voltage line provides a bypass capacitance between said first and said second reference voltages.
Continuing with the IC design featuring shielding meshes and reference voltage lines, at least one additional reference voltage line providing the first reference voltage is inserted between adjacent lines carrying the second reference voltage within the shielding mesh. This extra line creates bypass capacitance between the two reference voltages, which helps to filter noise and stabilize voltage levels within the IC.
6. An IC as in claim 1 , wherein said first double layer shielding mesh is in the first layer and the second layer of said IC and wherein at least the first portion of said first single layer shielding mesh is in one of said first and said second layers and wherein at least a second portion of said first single layer shielding mesh is in a third layer of said IC.
In the IC shielding configuration, the double-layer mesh exists within both the first and second layers of the IC. The single-layer shielding mesh has at least one portion within either the first or second layer, and another portion positioned within a third layer. This multi-layered arrangement ensures wider coverage and enhanced shielding effectiveness throughout the integrated circuit.
7. A method to design an integrated circuit (IC), said method comprising: creating, using a processor, a shielding mesh having at least a first portion disposed in a first layer of said IC and at least a second portion disposed in said first layer and a second layer, wherein said shielding mesh comprises a first single layer shielding mesh and a first double layer shielding mesh which is coupled to said first single layer shielding mesh; creating at least a first signal line having a first unshielded portion, which is disposed in a first region of said IC which is adjacent to said first single layer shielding mesh, and having a first shielded portion which is disposed in said first single layer shielding mesh, and having a second shielded portion which is disposed in said first double layer shielding mesh.
A method for designing an IC involves creating a shielding mesh in software, with a single-layer section in one layer and a double-layer section spanning two layers and connected to the single-layer section. The method further includes creating a signal line that has an unshielded segment near the single-layer mesh, a shielded segment within the single-layer mesh, and a second shielded segment within the double-layer mesh, using a processor to define these structures in the IC layout.
8. The method of claim 7 , wherein said first signal line also comprises a third shielded portion which is disposed in a second single layer shielding mesh and a second unshielded portion which is disposed in a second region of said IC which is adjacent to said second single layer shielding mesh.
Expanding upon the IC design method, the signal line also includes a third shielded segment within a second single-layer shielding mesh, and a second unshielded segment placed next to this second single-layer mesh. This step creates additional shielding around the signal line in another area of the integrated circuit.
9. The method of claim 8 , wherein said shielding mesh comprises a second double layer shielding mesh which is coupled to said second single layer shielding mesh and wherein said first signal line comprises a fourth shielded portion which is disposed in said second double layer shielded mesh.
Further expanding the IC design method, the shielding mesh includes a second double-layer shielding mesh linked to the second single-layer shielding mesh. Additionally, the signal line incorporates a fourth shielded portion within this second double-layer shielding mesh. This process results in increased signal shielding via the double layer mesh.
10. The method of claim 8 , wherein each of said first single layer shielding mesh, said first double layer shielding mesh, and said second single layer shielding mesh comprises a first plurality of reference voltage lines designed to provide a first reference voltage and a second plurality of reference voltage lines designed to provide a second reference voltage.
Using the IC design method described above, each shielding mesh layer (first single, first double, and second single) are constructed from alternating lines carrying two different reference voltages (e.g., ground and power). This reference voltage line arrangement is designed to create a more effective shielding structure by reducing noise coupling in the IC.
11. The method of claim 10 , further comprising: at least one reference voltage line, designed to provide said first reference voltage, disposed between a pair of adjacent second plurality of reference voltage lines in said shielding mesh, wherein said at least one reference voltage line provides a bypass capacitance between said first and said second reference voltages.
In the IC design method incorporating shielding meshes and reference voltage lines, the method includes creating at least one additional reference voltage line providing the first reference voltage, positioned between adjacent lines with the second reference voltage within the shielding mesh. This creates bypass capacitance between the two reference voltages, designed to filter noise and stabilize voltage levels within the IC.
12. The method of claim 7 , wherein said first double layer shielding mesh is in the first layer and the second layer of said IC and wherein at least the first portion of said first single layer shielding mesh is in one of said first and said second layers and wherein at least a second portion of said first single layer shielding mesh is in a third layer of said IC.
Using the IC design method, the double-layer mesh occupies both the first and second layers of the IC. The single-layer shielding mesh has at least one portion in either the first or second layer and another portion in a third layer. This arrangement is designed to provide broad coverage and effective shielding throughout the integrated circuit during the design phase.
13. A non-transitory machine readable storage medium containing executable computer program instructions which when executed by a digital processing system cause said system to perform operations to design an integrated circuit (IC), the operations comprising: creating a shielding mesh having at least a first portion disposed in a first layer of said IC and at least a second portion disposed in said first layer and a second layer, wherein said shielding mesh comprises a first single layer shielding mesh and a first double layer shielding mesh which is coupled to said first single layer shielding mesh; creating at least a first signal line having a first unshielded portion, which is disposed in a first region of said IC which is adjacent to said first single layer shielding mesh, and having a first shielded portion which is disposed in said first single layer shielding mesh, and having a second shielded portion which is disposed in said first double layer shielding mesh.
A non-transitory computer-readable storage medium stores instructions for designing an IC. The instructions, when executed, cause the system to create a shielding mesh with a single-layer section in one layer and a double-layer section spanning two layers and connected to the single-layer section. The instructions also create a signal line with an unshielded segment near the single-layer mesh, a shielded segment within the single-layer mesh, and another shielded segment within the double-layer mesh.
14. The non-transitory machine readable storage medium of claim 13 , wherein said first signal line also comprises a third shielded portion which is disposed in a second single layer shielding mesh and a second unshielded portion which is disposed in a second region of said IC which is adjacent to said second single layer shielding mesh.
In addition to the instructions stored on the computer-readable medium for IC design, the stored instructions create a signal line that further includes a third shielded segment within a second single-layer shielding mesh, and a second unshielded segment located next to this second single-layer mesh. This generates additional shielding around the signal line.
15. The non-transitory machine readable storage medium of claim 14 , wherein said shielding mesh comprises a second double layer shielding mesh which is coupled to said second single layer shielding mesh and wherein said first signal line comprises a fourth shielded portion which is disposed in said second double layer shielded mesh.
Expanding on the instructions stored for IC design, the shielding mesh includes a second double-layer shielding mesh connected to the second single-layer shielding mesh. The signal line also incorporates a fourth shielded portion within this second double-layer shielding mesh, further increasing shielding capabilities.
16. The non-transitory machine readable storage medium of claim 14 , wherein each of said first single layer shielding mesh, said first double layer shielding mesh, and said second single layer shielding mesh comprises a first plurality of reference voltage lines designed to provide a first reference voltage and a second plurality of reference voltage lines designed to provide a second reference voltage.
In the IC design instructions stored on a computer-readable medium, each shielding mesh layer (first single, first double, and second single) are constructed from alternating lines carrying two different reference voltages (e.g., ground and power), designed to create a more effective shielding structure by reducing noise coupling.
17. The non-transitory machine readable storage medium of claim 16 , further comprising instructions that cause the data processing system to perform operations comprising creating at least one reference voltage line designed to provide said first reference voltage, disposed between a pair of adjacent second plurality of reference voltage lines in said shielding mesh, wherein said at least one reference voltage line provides a bypass capacitance between said first and said second reference voltages.
The computer-readable medium storing IC design instructions further includes instructions to create at least one additional reference voltage line providing the first reference voltage, positioned between adjacent lines carrying the second reference voltage within the shielding mesh. This creates bypass capacitance between the two reference voltages, improving noise filtering and voltage stability within the IC.
18. The non-transitory machine readable storage medium of claim 13 , wherein said first double layer shielding mesh is in the first layer and the second layer of said IC and wherein at least the first portion of said first single layer shielding mesh is in one of said first and said second layers and wherein at least a second portion of said first single layer shielding mesh is in a third layer of said IC.
The computer-readable medium storing IC design instructions specifies that the double-layer mesh exists within both the first and second layers of the IC. The single-layer shielding mesh has at least one portion in either the first or second layer and another portion in a third layer, designed to provide enhanced coverage and effective shielding throughout the integrated circuit.
19. A data processing system to design an integrated circuit (IC) comprising: a memory; and a processor coupled to the memory, wherein the processor is configured to create a shielding mesh having at least a first portion disposed in a first layer of said IC and at least a second portion disposed in said first layer and a second layer, wherein said shielding mesh comprises a first single layer shielding mesh and a first double layer shielding mesh which is coupled to said first single layer shielding mesh, and the processor is configured to create at least a first signal line having a first unshielded portion, which is disposed in a first region of said IC which is adjacent to said first single layer shielding mesh, and having a first shielded portion which is disposed in said first single layer shielding mesh, and having a second shielded portion which is disposed in said first double layer shielding mesh.
A data processing system designs an IC, having memory and a processor. The processor creates a shielding mesh with a single-layer section in one layer and a double-layer section spanning two layers connected to the single-layer section. The processor also creates a signal line having an unshielded segment near the single-layer mesh, a shielded segment within the single-layer mesh, and another shielded segment within the double-layer mesh.
20. The data processing system of claim 9 , wherein said first signal line also comprises a third shielded portion which is disposed in a second single layer shielding mesh and a second unshielded portion which is disposed in a second region of said IC which is adjacent to said second single layer shielding mesh.
In the data processing system for IC design, the processor further creates a signal line that includes a third shielded segment within a second single-layer shielding mesh and a second unshielded segment placed adjacent to the second single-layer mesh. This process helps improve the shielding of the signal line.
Unknown
November 4, 2014
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.