Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A device comprising: a first terminal for a first clock signal: a second terminal for a second clock signal that is substantially complementary to the first clock signal; a third terminal for a third clock signal; a fourth terminal for a fourth clock signal that is substantially complementary to the third clock signal; a first logic gate performing a first logic operation on the first and third clock signals to produce a first intermediate signal; a second logic gate performing a second logic operation on the second and fourth clock signals to produce a second intermediate signal; a first delay circuit delaying the first intermediate signal to produce a third intermediate signal; a second delay circuit delaying the second intermediate signal to produce a fourth intermediate signal; and a first output circuit coupled to the first and second delay circuits to produce the third and fourth clock signals respectively at the third and fourth terminals.
A clock generator has four clock signal output terminals. The first terminal outputs a first clock signal, and the second outputs a second clock signal that is the inverse (complement) of the first. The third and fourth terminals output a third and fourth clock signal, respectively, where the fourth is the inverse of the third. The generator uses a first logic gate (like an OR gate) combining the first and third clock signals to create a first intermediate signal. Similarly, a second logic gate combines the second and fourth clock signals into a second intermediate signal. A first delay circuit delays the first intermediate signal to generate a third intermediate signal, and a second delay circuit delays the second intermediate signal to generate a fourth intermediate signal. The third and fourth intermediate signals drive an output circuit to produce the third and fourth clock signals.
2. The device according to claim 1 , further comprising: a third delay circuit delaying the first clock signal to produce a fifth intermediate signal; a fourth delay circuit delaying the second clock signal to produce a sixth intermediate signal; and a second output circuit coupled to the third and fourth delay circuits to produce the first and second clock signals respectively at the first and second terminals.
In addition to the clock generator described above with four clock signal output terminals and using logic gates and delay circuits to generate the third and fourth clock signals (claim 1), this version includes additional delay and output circuitry to refine the first and second clock signals. A third delay circuit delays the first clock signal to create a fifth intermediate signal, and a fourth delay circuit delays the second clock signal to create a sixth intermediate signal. A second output circuit then uses the fifth and sixth intermediate signals to produce the first and second clock signals, refining their timing.
3. The device according to claim 1 , wherein the first output circuit comprises an SR flip-flop circuit including a set node, a reset node, a true output node and a complementary output node, the set and reset nodes being supplied respectively with the third and fourth intermediate signals, and the true and complementary output nodes being coupled respectively to the fourth and third terminals.
In the clock generator that outputs four clock signals using logic gates and delay circuits (claim 1), the first output circuit (that generates the third and fourth clock signals) is specifically implemented using an SR flip-flop. The SR flip-flop has a set input, a reset input, a true output, and a complementary output. The third intermediate signal (delayed version of the first/third clock signal combination) is fed into the set input, and the fourth intermediate signal (delayed version of the second/fourth clock signal combination) is fed into the reset input. The true output of the flip-flop becomes the fourth clock signal output, and the complementary output becomes the third clock signal output.
4. The device according to claim 1 , wherein the first and second logic gates comprises an OR gate.
In the clock generator using logic gates and delay circuits to generate four clock signals (claim 1), the first and second logic gates, which combine clock signals, are specifically OR gates. Therefore the first OR gate combines the first and third clock signals to create the first intermediate signal, and the second OR gate combines the second and fourth clock signals to create the second intermediate signal.
5. The device according to claim 1 , wherein each of the first and second delay circuits presents signal delay time that is greater than a half of one cycle period of first clock signal.
In the clock generator that uses logic gates and delay circuits to generate four clock signals (claim 1), the first and second delay circuits introduce a delay that is longer than half the cycle time of the first clock signal. This means the delay circuits substantially shift the phase of the intermediate signals they process.
6. The device according to claim 2 , wherein each of the first and second delay circuits presents signal delay time that is greater than a half of one cycle period of the first clock signal and each of the third and fourth delay circuits presents a signal delay time that is substantially equal to a half of one cycle period of the first clock signal.
Expanding on the clock generator with added delay circuits refining the first and second clock signals (claim 2), the first and second delay circuits (affecting the third and fourth clock signals) each have a delay longer than half of the first clock signal's cycle time. Further, the third and fourth delay circuits (affecting the first and second clock signals), each have a delay approximately equal to half of the first clock signal's cycle time.
7. The device according to claim 2 , wherein each of the first and second output circuit comprises a set node, a reset node, a true output node and a complementary output node to serve as an SR flip-flop circuit, the set nodes of the first and second output circuits being supplied respectively with the third and fifth intermediate signals, the reset nodes of the first and second output circuits being supplied respectively with the fourth and sixth intermediate signals, the true output nodes of the first and second output circuits being coupled respectively to the fourth and second terminals, and the complementary output nodes of the first and second output circuits being coupled respectively to the third and first terminals.
In the clock generator with additional delay circuits refining the first and second clock signals (claim 2), both the first and second output circuits (generating clock signals) are implemented using SR flip-flops. Each flip-flop has a set input, a reset input, a true output, and a complementary output. The set input of the first output circuit (generating the third and fourth clock signals) receives the third intermediate signal. The reset input of the first output circuit receives the fourth intermediate signal. The true output becomes the fourth clock signal output, and the complementary output becomes the third clock signal output. The second output circuit (generating the first and second clock signals) is wired similarly, with the set input receiving the fifth intermediate signal, the reset input receiving the sixth intermediate signal, the true output becoming the second clock signal output, and the complementary output becoming the first clock signal output.
8. The device according to claim 2 , wherein each of the first and second logic gates comprises an OR gate.
In the clock generator that uses additional delay circuits for the first and second clock signals (claim 2), the first and second logic gates, which combine the clock signals, are OR gates. This means the OR gates combine the first/third and second/fourth clock signals, respectively.
9. The device according to claim 1 , further comprising: a first slave logic circuit including the first logic gate and the second logic gate; a first sub-circuit including the first delay circuit, the second delay circuit, and the first output circuit; and wherein the first slave sub-circuit producing the third clock signal that is substantially equal in frequency to the first clock signal and that differs in phase from the first clock signal by a first value that is smaller than a half of one cycle period of the first clock signal.
The clock generator with four clock signal outputs (claim 1) includes a "slave" sub-circuit. This sub-circuit contains the first and second logic gates (combining clock signals), the first and second delay circuits, and the first output circuit (generating the third and fourth clock signals). The slave sub-circuit generates the third clock signal, which has essentially the same frequency as the first clock signal but is phase-shifted by an amount less than half the cycle time of the first clock signal.
10. The device according to claim 9 , further comprising: a master sub-circuit generating the first clock signal at the first terminal and the second clock signal at the second terminal, the first clock signal being substantially complementary to the second clock signal.
Building on the clock generator with the slave sub-circuit (claim 9), this includes a "master" sub-circuit that generates the first and second clock signals. The first and second clock signals are complementary (inverses) of each other. The master sub-circuit feeds the clock signals into the slave sub-circuit described previously.
11. The device according to claim 9 , further comprising a second slave logic circuit including a third logic gate receiving the first clock signal and a fifth clock signal, and including a fourth logic gate receiving the second clock signal and a sixth clock signal; a second sub-circuit producing the fifth clock signal and the sixth clock signal, the fifth clock signal being substantially complementary to the sixth clock signal, the first and fifth clock signals being substantially equal in frequency to each other and differing in phase from each other by a second value that is smaller than a half of one cycle period of the first clock signal.
Extending the clock generator with master/slave subcircuits (claim 9), this version adds a *second* slave sub-circuit. This second slave sub-circuit includes third and fourth logic gates. The third gate receives the first clock signal and a fifth clock signal. The fourth gate receives the second clock signal and a sixth clock signal. The second slave sub-circuit generates the fifth and sixth clock signals, which are complementary. The first and fifth clock signals have the same frequency, but are phase-shifted by a value smaller than half the cycle time of the first clock signal.
12. The device according to claim 11 , wherein the first value is different from the second value.
In the clock generator with two slave sub-circuits (claim 11), the phase shift introduced by the *first* slave sub-circuit is different from the phase shift introduced by the *second* slave sub-circuit.
13. The device according to claim 9 , further comprising a second slave logic circuit including a third logic gate receiving the third clock signal and a fifth clock signal, and including a fourth logic gate receiving the fourth clock signal and a sixth clock signal; a second sub-circuit producing the fifth clock signal and the sixth clock signal, the fifth clock signal being substantially complementary to the sixth clock signal, the first and fifth clock signals being substantially equal in frequency to each other and differing in phase from each other by a second value that is smaller than a half of one cycle period of the first clock signal.
Expanding on the clock generator with the master/slave configuration (claim 9), this version has a second slave logic circuit. The third logic gate of the second slave circuit receives the *third* clock signal (output of the first slave circuit) and a fifth clock signal. The fourth logic gate receives the fourth clock signal (output of the first slave circuit) and a sixth clock signal. The second sub-circuit generates the fifth and sixth clock signals, which are complementary. The first and fifth clock signals have the same frequency but are phase-shifted by a value smaller than half the cycle time of the first clock signal.
14. The device according to claim 13 , wherein the first value is different from the second value.
In the clock generator with slave sub-circuits (claim 13), the phase shift introduced by the first slave sub-circuit differs from the phase shift introduced by the second slave sub-circuit.
15. The device according to claim 1 , further comprising: a control unit; a memory unit; a bus interconnecting the memory unit and memory unit to each other; the first terminal coupled to the control unit and the memory unit to convey the first clock signal, the control unit accessing to the memory unit through the bus in response to the first clock signal; the third terminal coupled to the memory unit to convey the third clock signal, the memory unit supplying data to the control unit through the bus in response to the second clock signal.
The clock generator with four output clock signals (claim 1) is integrated into a larger system, including a control unit, a memory unit, and a bus connecting them. The first clock signal is provided to both the control unit and the memory unit. The control unit accesses the memory unit via the bus, triggered by the first clock signal. The third clock signal is provided to the memory unit. The memory unit provides data to the control unit over the bus, triggered by the second clock signal.
16. The device according to claim 15 , further comprising: a first clock generator generating the first clock signal to be supplied to the first terminal.
Building on the integrated system with the clock generator providing the first clock signal (claim 15), the system includes a *separate* clock generator dedicated to creating the first clock signal, which is then supplied to the first terminal.
17. The device according to claim 16 , wherein the first clock generator comprising: a third delay circuit delaying the first clock signal to produce a fifth intermediate signal; a fourth delay circuit delaying a second clock signal to produce a sixth intermediate signal; and a second output circuit coupled to the third and fourth delay circuits to receive the fifth and sixth intermediate signals and to produce the first and second clock signals respectively.
Elaborating on the system with a separate clock generator (claim 16), this generator consists of a third delay circuit delaying the first clock signal to produce a fifth intermediate signal, a fourth delay circuit delaying the second clock signal to produce a sixth intermediate signal, and a second output circuit coupled to the third and fourth delay circuits to receive the fifth and sixth intermediate signals and generate the first and second clock signals.
18. The device according to claim 17 , wherein each of the third and fourth delay circuit presents delay time that is substantially equal to a half of one cycle period of the first clock signal, and wherein each of the first and second delay circuits presents delay time that is substantially equal to a sum of the first value and a half of one cycle period of the first clock signal.
Building on the clock generator with dedicated clock signal generation (claim 17), the third and fourth delay circuits each introduce a delay equal to approximately half the cycle time of the first clock signal. The first and second delay circuits (part of the main clock generator loop from claim 1) each introduce a delay equal to the sum of the phase shift value (introduced in claim 9) and half the cycle time of the first clock signal.
19. The device according to claim 1 , wherein each of the first and second delay circuits has delay time that is variable in response to configuration data.
In the clock generator with four clock outputs (claim 1), the first and second delay circuits have *adjustable* delay times. The amount of delay can be changed based on configuration data.
20. The device according to claim 1 , wherein each of the first and second delay circuits comprises a capacitor and a charging/discharging circuit supplying a charging/discharging current to the capacitor, a capacitance value of the capacitor and the charging/discharging current of the charging/discharging circuit being configured to be varied in response to configuration data.
In the clock generator with adjustable delay (claim 19), the first and second delay circuits are implemented using capacitors and charging/discharging circuits. These circuits supply current to charge/discharge the capacitor. The capacitance of the capacitor and the charging/discharging current are adjusted based on configuration data, allowing for variable delay.
21. The device according to claim 1 , further comprising: a fifth terminal for a fifth clock signal; a sixth terminal for a sixth clock signal that is substantially complementary to the fifth clock signal; a third logic gate performing the first logic operation on the first and fifth clock signals to produce a fifth intermediate signal; a fourth logic gate performing the second logic operation on the second and sixth clock signals to produce a sixth intermediate signal; a third delay circuit delaying the fifth intermediate signal to produce a seventh intermediate signal; a fourth delay circuit delaying the sixth intermediate signal to produce an eighth intermediate signal; and a second output circuit coupled to the third and fourth delay circuits to receive the seventh and eight intermediate signals and to produce the fifth and sixth clock signals respectively at the fifth and sixth terminals.
In addition to the basic clock generator setup (claim 1), this version adds two more clock signal outputs. A fifth terminal outputs a fifth clock signal, and a sixth terminal outputs a sixth clock signal that is the inverse of the fifth. The clock generator includes a third logic gate combining the first and fifth clock signals to generate a fifth intermediate signal. A fourth logic gate combines the second and sixth clock signals to produce a sixth intermediate signal. A third delay circuit delays the fifth intermediate signal to generate a seventh intermediate signal, and a fourth delay circuit delays the sixth intermediate signal to generate an eighth intermediate signal. The seventh and eighth intermediate signals drive a second output circuit to produce the fifth and sixth clock signals.
22. The device according to claim 1 , further comprising: a fifth terminal for a fifth clock signal; a sixth terminal for a sixth clock signal that is substantially complementary to the fifth clock signal; a third logic gate performing the first logic operation on the third and fifth clock signals to produce a fifth intermediate signal; a fourth logic gate performing the second logic operation on the fourth and sixth clock signals to produce a sixth intermediate signal; a third delay circuit delaying the fifth intermediate signal to produce a seventh intermediate signal; a fourth delay circuit delaying the sixth intermediate signal to produce an eighth intermediate signal; and a second output circuit coupled to the third and fourth delay circuits to receive the seventh and eight intermediate signals and to produce the fifth and sixth clock signals respectively at the fifth and sixth terminals.
In addition to the basic clock generator setup (claim 1), this version adds two more clock signal outputs. A fifth terminal outputs a fifth clock signal, and a sixth terminal outputs a sixth clock signal that is the inverse of the fifth. The clock generator includes a third logic gate combining the *third* (output from the first stage) and fifth clock signals to generate a fifth intermediate signal. A fourth logic gate combines the *fourth* (output from the first stage) and sixth clock signals to produce a sixth intermediate signal. A third delay circuit delays the fifth intermediate signal to generate a seventh intermediate signal, and a fourth delay circuit delays the sixth intermediate signal to generate an eighth intermediate signal. The seventh and eighth intermediate signals drive a second output circuit to produce the fifth and sixth clock signals.
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November 11, 2014
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