Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method for computing, comprising: running software including a plurality of virtual machines on a computer having one or more cores and a memory, such that different ones of the virtual machines are swapped out of operation on the cores at different times; assigning to the virtual machines, by operation of the software, respective interrupt addresses in the memory; upon occurrence on an input/output (I/O) device connected by a bus to the computer of an event that would cause the I/O device to direct an interrupt to a given virtual machine, identifying at the I/O device whether the given virtual machine is active or swapped out, and deciding, when the given virtual machine is swapped out of operation, not to send an interrupt directly to the CPU but to write an interrupt message from the I/O device to a respective interrupt address that is assigned to the given virtual machine in the memory, or to raise the hardware interrupt immediately when the given virtual machine is active; and upon activating the given virtual machine on a given core after writing of the interrupt message, copying, by operation of the software, a context of the given virtual machine from the memory to the given core and automatically raising a hardware interrupt on the given core responsively to the interrupt message in the memory.
A system runs virtual machines on a computer with multiple cores and memory. Each VM is assigned a specific interrupt address in memory. When an I/O device (connected by a bus) needs to interrupt a VM, it checks if that VM is currently active. If the VM is inactive (swapped out), the I/O device writes an interrupt message to the VM's assigned memory address instead of directly interrupting the CPU. When the VM is later reactivated on a core, its context is loaded from memory, and the system automatically raises a hardware interrupt on that core based on the interrupt message previously written to memory. If the VM is active the I/O device raises the hardware interrupt immediately.
2. The method according to claim 1 , wherein the I/O device comprises a network interface controller (NIC), and wherein the event comprises receiving at the NIC a data packet directed to the given virtual machine.
Using the system described in claim 1, the I/O device is a network interface controller (NIC). The event that triggers the interrupt is the NIC receiving a data packet intended for a specific virtual machine. When the virtual machine is swapped out, instead of immediately signaling the CPU, the NIC writes a message to the virtual machine's designated interrupt address in memory. When the VM is later reactivated, the system uses this message to trigger a hardware interrupt.
3. The method according to claim 1 , and comprising passing information from the computer to the device as to which of the virtual machines are active and which are swapped out, wherein the device decides whether to write the interrupt message or to raise the hardware interrupt responsively to the information.
Using the system described in claim 1, the computer system actively communicates information to the I/O device about which virtual machines are currently active or swapped out. The I/O device uses this information to decide whether to write an interrupt message to memory (if the VM is swapped out) or to immediately raise a hardware interrupt (if the VM is active). This allows the I/O device to make intelligent decisions about interrupt handling based on the VM's current state.
4. The method according to claim 1 , wherein the event causing the device to write the interrupt message is a low-priority event type, and wherein the method comprises, upon the occurrence at the device of events of a high-priority event type, raising the hardware interrupt for service by the given virtual machine immediately even when the given virtual machine is swapped out.
Using the system described in claim 1, the event causing the device to write the interrupt message is a low-priority event. However, if a high-priority event occurs that requires interrupting the VM, the I/O device bypasses the memory write and raises the hardware interrupt immediately, even if the virtual machine is swapped out. This ensures timely handling of critical events regardless of the VM's active status.
5. The method according to claim 1 , wherein automatically raising the hardware interrupt comprises copying the interrupt message from the respective interrupt address to an interrupt status register on the given core.
Using the system described in claim 1, automatically raising the hardware interrupt when a VM is activated involves copying the interrupt message from the VM's assigned interrupt address in memory to an interrupt status register on the core where the VM is being activated. This transfer of the interrupt message triggers the interrupt handling process on the core.
6. The method according to claim 5 , wherein copying the interrupt message comprises taking a logical OR between a first value stored in the respective interrupt address and a second value already held in the interrupt status register.
Using the system described in claim 5, when the interrupt message is copied from the memory address to the core's interrupt status register, a logical OR operation is performed. This combines the new interrupt information (from the memory address) with any existing interrupt information already present in the interrupt status register, ensuring that all pending interrupts are properly handled.
7. Computing apparatus, comprising: a central processing unit (CPU) comprising one or more computing cores, configured to run software including a plurality of virtual machines, such that different ones of the virtual machines are swapped out of operation on the cores at different times; a memory, connected to the computing cores, in which respective interrupt addresses are assigned by operation of the software to the virtual machines; and an input/output (I/O) device, which is connected by a bus to the cores and the memory and is configured, upon occurrence of an event that would cause the I/O device to direct an interrupt to a given virtual machine, to identify at the I/O device whether the given virtual machine is active or swapped out, and to decide, when the given virtual machine is swapped out of operation, not to send an interrupt directly to the CPU but to write an interrupt message to a respective interrupt address that is assigned to the given virtual machine in the memory, or to raise the hardware interrupt immediately when the given virtual machine is active, wherein the cores are configured, upon activating the given virtual machine on a given core after writing of the interrupt message, to copy, by operation of the software, a context of the given virtual machine from the memory to the given core and to automatically raise a hardware interrupt on the given core responsively to the interrupt message in the memory.
A computing system includes a CPU with one or more cores that runs a plurality of virtual machines, swapping them in and out of operation. The system has memory where interrupt addresses are assigned to each VM by the software. An I/O device connected by a bus to the cores and memory detects events requiring interrupts for VMs. If a VM is inactive, the I/O device writes an interrupt message to the VM's assigned memory address instead of sending a direct interrupt to the CPU. When the VM is later activated, the core copies the VM's context from memory and raises a hardware interrupt based on the message in the memory. If the VM is active the I/O device raises the hardware interrupt immediately.
8. The apparatus according to claim 7 , wherein the I/O device comprises a network interface controller (NIC), and wherein the event comprises receiving at the NIC a data packet directed to the given virtual machine.
Using the apparatus described in claim 7, the I/O device is a network interface controller (NIC). The event triggering the interrupt is the NIC receiving a data packet for a specific virtual machine. When that virtual machine is swapped out, the NIC writes an interrupt message to the virtual machine's designated interrupt address in memory rather than immediately interrupting the CPU. This message will trigger an interrupt when the VM is reactivated.
9. The apparatus according to claim 7 , wherein the I/O device is configured to receive information from the cores as to which of the virtual machines are active and which are swapped out, and to decide whether to write the interrupt message or to raise the hardware interrupt responsively to the information.
Using the apparatus described in claim 7, the I/O device receives information from the cores indicating which virtual machines are active and which are swapped out. The I/O device uses this information to determine whether to immediately raise a hardware interrupt or to write an interrupt message to the VM's memory address, making the interrupt handling process more efficient.
10. The apparatus according to claim 7 , wherein the event causing the device to write the interrupt message is a low-priority event type, and wherein the device is configured, upon the occurrence at the device of events of a high-priority event type, to raise the hardware interrupt for service by the given virtual machine immediately even when the given virtual machine is swapped out.
Using the apparatus described in claim 7, the event causing the device to write the interrupt message to memory is a low-priority event. However, if a high-priority event occurs that requires interrupting a swapped-out VM, the device bypasses the memory write and immediately raises the hardware interrupt. This ensures that critical events are handled promptly, regardless of the VM's active status.
11. The apparatus according to claim 7 , wherein the cores comprise respective interrupt status registers and are configured, upon activating the given virtual machine, to copy the interrupt message from the respective interrupt address to an interrupt status register on the given core.
Using the apparatus described in claim 7, the cores contain interrupt status registers. When a virtual machine is activated, the system copies the interrupt message from the VM's assigned memory address to the interrupt status register on the core where the VM is being activated. This action triggers the interrupt handling mechanism on the core, ensuring that pending interrupts are processed.
12. The apparatus according to claim 11 , wherein the cores are configured, upon copying the interrupt message to the interrupt status register, to take a logical OR between a first value stored in the respective interrupt address and a second value already held in the interrupt status register.
Using the apparatus described in claim 11, upon copying the interrupt message from the interrupt address to the core's interrupt status register, the system performs a logical OR operation between the value in the interrupt address and the value already in the interrupt status register. This combines the new interrupt information with any existing pending interrupts, ensuring that all interrupt events are properly addressed.
Unknown
November 11, 2014
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