Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A computer-implemented method of generating a net list, the method comprising: generating logical data for each of portions corresponding to blocks of a register transfer level description relevant to operation of a gate logic circuit, accounting for an order of priority in the register transfer level description, based on a source code comprising the register transfer level description; generating one or more constraint conditions designating circuit data which satisfies a condition among a plurality of gate level circuit data logically equivalent to the logical data for each of the portions, based on the source code, the generating the one or more constraint conditions comprising setting a fixing attribute for at least one of the portions describing an AND logic operation on an asynchronous signal or a multi-cycle signal, and an enable signal or a select signal, the fixing attribute configured to exclude performance of optimization on the at least one of the portions; and generating the net list based on optimization of the logical data under the one or more constraint conditions including the fixing attribute, the method performed programmatically by a design system that comprises one or more computers.
A computer-implemented method for generating a netlist from a register transfer level (RTL) description. The method involves: (1) generating logical data representing blocks of the RTL code, considering the order of operations; (2) creating constraint conditions to specify acceptable gate-level circuit implementations equivalent to the logical data. This includes setting a "fixing attribute" for portions with AND logic operations on asynchronous/multi-cycle signals, enable/select signals to prevent optimization on these specific portions; and (3) generating the final netlist by optimizing the logical data while adhering to these constraints, including the fixing attributes. The method is performed automatically by a circuit design system.
2. The net list generating method of claim 1 , wherein at least some of the source code indicates the one or more constraint conditions in the register transfer level description.
The netlist generation method as described where at least some of the RTL source code includes the constraint conditions directly embedded within the register transfer level description. This allows the designer to explicitly specify optimization boundaries and signal handling rules within the RTL code itself, thus providing better control over the final netlist generation.
3. The net list generating method of claim 1 , wherein the one or more constraint conditions comprise information on a location where a plurality of signals, each respectively driven by one of a plurality of different clocks, coexist together in the logical data for each of the portions, and the generating the net list generates the net list with the location excluded from a target for optimization.
The netlist generation method as described where the constraint conditions include information about locations where signals driven by different clocks converge. The method then excludes these locations from optimization during netlist generation. This prevents the introduction of timing errors or metastability issues that can arise when optimizing circuits with multiple clock domains.
4. The net list generating method of claim 1 , wherein the source code comprises timing constraint information designating a multi-cycle path signal, the one or more constraint conditions comprise information on a location where the multi-cycle path signal is inputted in the logical data for each of the portions, and the generating the net list generates the net list with the location excluded from a target for optimization.
The netlist generation method as described where the RTL source code includes timing constraints for multi-cycle paths, and the constraint conditions include the locations where these multi-cycle path signals are input. The method excludes these locations from optimization during netlist generation. This preserves the intended timing behavior of multi-cycle paths and prevents incorrect optimization.
5. The net list generating method of claim 1 , wherein the circuit data which satisfies the condition, designated by the one or more constraint conditions, is such that a signal designated by the one or more constraint conditions is inputted to a second logic circuit which outputs a signal to be inputted to a first logic circuit of the circuit data.
The netlist generation method as described where the constraint conditions specify that a signal subject to the constraint must be input to a second logic circuit, which in turn drives the input of a first logic circuit. This creates a specific circuit topology enforced by the constraints, ensuring particular signal flow characteristics are maintained throughout the optimization process.
6. A non-transitory, computer-readable storage medium having stored thereon a net list generating program that, when executed by an electronic computer, causes the computer to execute functions comprising: generating logical data for each of portions corresponding to blocks of a register transfer level description relevant to operation of a gate logic circuit, accounting for an order of priority in the register transfer level description, based on source code comprising the register transfer level description; generating one or more constraint conditions designating circuit data which satisfies a condition among a plurality of gate level circuit data logically equivalent to the logical data for each of the portions, based on the source code, the generating the one or more constraint conditions comprising setting a fixing attribute for at least one of the portions describing an AND logic operation on an asynchronous signal or a multi-cycle signal, and an enable signal or a select signal the fixing attribute to configured to exclude performance of optimization on the at least one of the portions; and generating the net list based on optimization of the logical data under the one or more constraint conditions including the fixing attribute.
A non-transitory computer-readable storage medium storing a netlist generation program. When executed, the program: (1) generates logical data for each block of an RTL description relevant to gate logic circuit operation, considering the order of priority in the RTL; (2) generates constraint conditions for gate-level circuit data that is logically equivalent to the logical data, including setting a "fixing attribute" to prevent optimization on portions describing AND logic on asynchronous/multi-cycle signals, enable/select signals; and (3) generates the final netlist by optimizing the logical data subject to these constraints, including the fixing attribute.
7. The storage medium of claim 6 , wherein at least some of the source code indicates the one or more constraint conditions in the register transfer level description.
The storage medium as described where at least some of the RTL source code indicates the constraint conditions directly embedded within the register transfer level description. This allows the designer to explicitly specify optimization boundaries and signal handling rules within the RTL code itself, thus providing better control over the final netlist generation.
8. The storage medium of claim 6 , wherein the one or more constraint conditions comprise information on a location where a plurality of signals, each respectively driven by one of a plurality of different clocks, coexist together in the logical data for each of the portions, and the generating the net list generates the net list with the location excluded from a target for optimization.
The storage medium as described where the constraint conditions include information about locations where signals driven by different clocks converge. The method then excludes these locations from optimization during netlist generation. This prevents the introduction of timing errors or metastability issues that can arise when optimizing circuits with multiple clock domains.
9. The storage medium of claim 6 , wherein the source code comprises timing constraint information designating a multi-cycle path signal, the one or more constraint conditions comprise information on a location where the multi-cycle path signal is inputted in the logical data for each of the portions, and the generating the net list generates the net list with the location excluded from a target for optimization.
The storage medium as described where the RTL source code includes timing constraints for multi-cycle paths, and the constraint conditions include the locations where these multi-cycle path signals are input. The method excludes these locations from optimization during netlist generation. This preserves the intended timing behavior of multi-cycle paths and prevents incorrect optimization.
10. The storage medium of claim 6 , wherein the circuit data which satisfies the condition, designated by the one or more constraint conditions, is such that a signal designated by the one or more constraint conditions is inputted to a second logic circuit which outputs a signal to be inputted to a first logic circuit of the circuit data.
The storage medium as described where the constraint conditions specify that a signal subject to the constraint must be input to a second logic circuit, which in turn drives the input of a first logic circuit. This creates a specific circuit topology enforced by the constraints, ensuring particular signal flow characteristics are maintained throughout the optimization process.
11. A net list design system including one or more computing devices comprising: a logical data generator configured to generate logical data for each of portions corresponding to blocks of a register transfer level description relevant to operation of a gate logic circuit, accounting for an order of priority in the register transfer level description, based on source code comprising the register transfer level description; a constraint-condition unit configured to generate one or more constraint conditions designating circuit data which satisfies a condition among a plurality of gate level circuit data logically equivalent to the logical data for each of the portions, based on the source code, the one or more constraint conditions comprising a fixing attribute for at least one of the portions describing an AND logic operation on an asynchronous signal or a multi-cycle signal, and an enable signal or a select signal, the fixing attribute configured to inhibit performance of optimization on the at least one of the portions; and an optimization unit configured to generate the net list based on the logical data under the one or more constraint conditions including the fixing attribute.
A netlist design system including one or more computers comprising: (1) a logical data generator that creates logical data for each block of an RTL description, accounting for priority, based on the RTL source code; (2) a constraint condition unit that generates constraint conditions for gate-level circuit data equivalent to the logical data. The conditions include a "fixing attribute" to prevent optimization on portions with AND logic on asynchronous/multi-cycle signals, enable/select signals; and (3) an optimization unit that generates the netlist based on the logical data, subject to the constraint conditions, including the fixing attribute.
12. The net list design system of claim 11 , wherein at least some of the source code indicates the one or more constraint conditions in the register transfer level description.
The netlist design system as described where at least some of the RTL source code indicates the constraint conditions directly embedded within the register transfer level description. This allows the designer to explicitly specify optimization boundaries and signal handling rules within the RTL code itself, thus providing better control over the final netlist generation.
13. The net list design system of claim 11 , wherein the one or more constraint conditions comprise information on a location where a plurality of signals, each respectively driven by one of a plurality of different clocks, coexist together in the logical data for each of the portions, and the optimization unit generates the net list with the location excluded from a target for optimization.
The netlist design system as described where the constraint conditions include information about locations where signals driven by different clocks converge. The optimization unit generates the netlist while excluding these locations from optimization. This prevents the introduction of timing errors or metastability issues that can arise when optimizing circuits with multiple clock domains.
14. The net list design system of claim 11 , wherein the source code comprises timing constraint information designating a multi-cycle path signal, the one or more constraint conditions comprise information on a location where the multi-cycle path signal is inputted in the logical data for each of the portions, and the optimization unit generates the net list with the location excluded from a target for optimization.
The netlist design system as described where the RTL source code includes timing constraints for multi-cycle paths, and the constraint conditions include the locations where these multi-cycle path signals are input. The optimization unit generates the netlist while excluding these locations from optimization. This preserves the intended timing behavior of multi-cycle paths and prevents incorrect optimization.
15. The net list design system of claim 11 , wherein the circuit data which satisfies the condition, designated by the one or more constraint conditions, is such that a signal designated by the one or more constraint conditions is inputted to a second logic circuit which outputs a signal to be inputted to a first logic circuit of the circuit data.
The netlist design system as described where the constraint conditions specify that a signal subject to the constraint must be input to a second logic circuit, which in turn drives the input of a first logic circuit. This creates a specific circuit topology enforced by the constraints, ensuring particular signal flow characteristics are maintained throughout the optimization process.
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November 25, 2014
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