Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A signal routing apparatus comprising: a delay locked loop to generate a plurality of phase displaced clock signals; and a phase controlled write circuit connected to said delay locked loop to store each of a plurality of signals received at the write circuit in response to different phase displaced clock signals received at the write circuit.
A signal routing device features a delay-locked loop (DLL) that generates multiple clock signals, each slightly out of phase with the others. A "phase-controlled write circuit" uses these phase-shifted clocks to store incoming signals. The circuit writes each signal in response to a specific, different phase of the DLL's clock outputs. This allows writing data at a high rate without requiring a very fast master clock.
2. The signal routing apparatus of claim 1 further comprising a register bank connected to said phase controlled write circuit, said register bank storing in parallel said plurality of signals.
In addition to the signal routing device with a delay-locked loop (DLL) generating phase-shifted clocks and a phase-controlled write circuit that stores incoming signals using those clocks (as described previously), this device also includes a register bank. This register bank is connected to the phase-controlled write circuit and stores all the incoming signals in parallel. This allows the signals to be quickly accessed and processed after they are written.
3. The signal routing apparatus of claim 1 in combination with a programmable logic device.
This combines the signal routing device, which includes a delay-locked loop (DLL) to generate multiple phase-shifted clock signals and a phase-controlled write circuit that stores signals based on these clocks (as described previously), with a programmable logic device (PLD). This allows the routing device to be customized or reconfigured for different applications by changing the programming of the PLD. The PLD could be used to control the write circuit or to process the routed signals.
4. The signal routing apparatus of claim 1 wherein said phase controlled write circuit includes a set of transistor columns, each transistor column of said set of transistor columns being responsive to two phase displaced clock signals of said plurality of phase displaced clock signals.
This signal routing device, containing a delay-locked loop (DLL) and a phase-controlled write circuit (as described previously), utilizes a specific architecture for the write circuit. The phase-controlled write circuit consists of multiple columns of transistors. Each transistor column is activated by a pair of the phase-shifted clock signals generated by the DLL. This allows fine-grained control over the timing of signal storage.
5. The signal routing apparatus of claim 4 wherein each transistor column of said set of transistor columns includes a subset of pull-up transistors connected to an output node, said subset of pull-up transistors processing a first phase displaced clock signal and a second phase displaced clock signal immediately adjacent to said first phase displaced clock signal.
Building upon the signal routing device with the phase-controlled write circuit comprised of transistor columns activated by phase-shifted clocks (as previously described), each transistor column contains a group of "pull-up" transistors connected to an output node. This subset of pull-up transistors are controlled by one phase-shifted clock signal and the immediately following, adjacent phase-shifted clock signal. This arrangement facilitates a controlled transition and avoids signal contention.
6. The signal routing apparatus of claim 5 wherein each transistor column of said set of transistor columns includes a subset of pull-down transistors connected to said output node, said subset of pull-down transistors processing a first phase displaced clock signal and a second phase displaced clock signal immediately adjacent to said first phase displaced clock signal.
Building upon the signal routing device with the phase-controlled write circuit comprised of transistor columns activated by phase-shifted clocks and pull-up transistors (as previously described), each transistor column *also* includes a group of "pull-down" transistors connected to the same output node. These pull-down transistors are controlled by the same pair of adjacent phase-shifted clock signals as the pull-up transistors. This complementary arrangement allows for precise control of the output signal level.
7. A signal routing apparatus comprising: a delay locked loop to generate a plurality of phase displaced clock signals; a phase controlled read circuit connected to the delay locked loop to sequentially route each of a plurality of signals received at the read circuit in response to different phase displaced clock signals received at the read circuit.
A signal routing device features a delay-locked loop (DLL) that generates multiple clock signals, each slightly out of phase. A "phase-controlled read circuit" uses these phase-shifted clocks to sequentially route a set of signals. The circuit reads each signal in response to a specific, different phase of the DLL's clock outputs. This allows reading data at a high rate without requiring a very fast master clock.
8. The signal routing apparatus of claim 7 wherein said phase controlled read circuit includes a set of transistor columns, each transistor column of said set of transistor columns being responsive to two phase displaced clock signals of said plurality of phase displaced clock signals.
This signal routing device, containing a delay-locked loop (DLL) and a phase-controlled read circuit (as described previously), utilizes a specific architecture for the read circuit. The phase-controlled read circuit consists of multiple columns of transistors. Each transistor column is activated by a pair of the phase-shifted clock signals generated by the DLL. This allows fine-grained control over the timing of signal retrieval.
9. The signal routing apparatus of claim 8 wherein each transistor column of said set of transistor columns includes a subset of pull-up transistors connected to an output node, said subset of pull-up transistors processing a first phase displaced clock signal and a second phase displaced clock signal immediately adjacent to said first phase displaced clock signal.
Building upon the signal routing device with the phase-controlled read circuit comprised of transistor columns activated by phase-shifted clocks (as previously described), each transistor column contains a group of "pull-up" transistors connected to an output node. This subset of pull-up transistors are controlled by one phase-shifted clock signal and the immediately following, adjacent phase-shifted clock signal. This arrangement facilitates a controlled transition and avoids signal contention.
10. The signal routing apparatus of claim 9 wherein each transistor column of said set of transistor columns includes a subset of pull-down transistors connected to said output node, said subset of pull-down transistors processing a first phase displaced clock signal and a second phase displaced clock signal immediately adjacent to said first phase displaced clock signal.
Building upon the signal routing device with the phase-controlled read circuit comprised of transistor columns activated by phase-shifted clocks and pull-up transistors (as previously described), each transistor column *also* includes a group of "pull-down" transistors connected to the same output node. These pull-down transistors are controlled by the same pair of adjacent phase-shifted clock signals as the pull-up transistors. This complementary arrangement allows for precise control of the output signal level.
11. A signaling system comprising: a transmitter comprising: a first delay locked loop to generate a set of phase displaced clock signals; a phase controlled read circuit to sequentially route a set of data signals received at the read circuit in response to said phase displaced clock signals; and a signaling buffer connected to said phase controlled read circuit to transmit said data signals; and a receiver comprising: a receiver buffer to receive a set of signals and produce a corresponding set of buffered signals; a second delay locked loop to generate a set of phase displaced clock signals; and a phase controlled write circuit connected to said receiver buffer and said delay locked loop to store said set of buffered signals in response to said phase displaced clock signals.
A signaling system comprises a transmitter and a receiver. The transmitter has a delay-locked loop (DLL) to generate phase-shifted clocks and a phase-controlled read circuit that uses these clocks to sequentially route data signals. A signaling buffer then transmits the data signals. The receiver has a buffer to receive signals, a second DLL to generate its own set of phase-shifted clocks, and a phase-controlled write circuit that uses *its* DLL's clocks to store the received signals. Thus, data is transmitted and received using phase-shifted clocks on both ends.
12. The signaling system of claim 11 further comprising a register bank connected to said phase controlled write circuit, said register bank storing in parallel said set of buffered signals.
In addition to the signaling system described above, featuring a transmitter with a DLL and phase-controlled read, and a receiver with a DLL and phase-controlled write, the receiver *also* includes a register bank. This register bank is connected to the receiver's phase-controlled write circuit and stores the received, buffered signals in parallel. This provides fast access to the received data.
13. The signaling system of claim 11 wherein said phase controlled read circuit includes a set of transistor columns, each transistor column of said set of transistor columns being responsive to two phase displaced clock signals of said set of phase displaced clock signals.
In the signaling system with a transmitter and receiver (as previously described), the transmitter's phase-controlled read circuit, which sequentially routes data using phase-shifted clocks, employs a specific design. The read circuit contains columns of transistors, each driven by two adjacent phase-shifted clock signals from the transmitter's DLL.
14. The signaling system of claim 13 wherein each transistor column of said set of transistor columns includes a subset of pull-up transistors connected to an output node, said subset of pull-up transistors processing a first phase displaced clock signal, a second phase displaced clock signal immediately adjacent to said first phase displaced clock signal, and a register bank signal.
Within the transmitter's phase-controlled read circuit, comprised of transistor columns driven by phase-shifted clocks (as previously described), each column contains pull-up transistors connected to an output. These pull-up transistors are controlled by a phase-shifted clock, its immediate neighbor, and a signal from a register bank (although a register bank is not explicitly mentioned in the claim 11 description, one can be inferred for storing the 'set of data signals').
15. The signaling system of claim 14 wherein each transistor column of said set of transistor columns includes a subset of pull-down transistors connected to said output node, said subset of pull-down transistors processing a first phase displaced clock signal, a second phase displaced clock signal immediately adjacent to said first phase displaced clock signal, and a register bank signal.
Within the transmitter's phase-controlled read circuit, comprised of transistor columns driven by phase-shifted clocks and containing pull-up transistors (as previously described), each column *also* has pull-down transistors connected to the same output. These pull-down transistors are controlled by a phase-shifted clock, its immediate neighbor, and a signal from a register bank (although a register bank is not explicitly mentioned in the claim 11 description, one can be inferred for storing the 'set of data signals').
16. The signaling system of claim 11 wherein said phase controlled write circuit includes a set of transistor columns, each transistor column of said set of transistor columns being responsive to two phase displaced clock signals of said set of phase displaced clock signals.
In the signaling system with a transmitter and receiver (as previously described), the receiver's phase-controlled write circuit, which stores received data using phase-shifted clocks, employs a specific design. The write circuit contains columns of transistors, each driven by two adjacent phase-shifted clock signals from the receiver's DLL.
17. The signaling system of claim 16 wherein each transistor column of said set of transistor columns includes a subset of pull-up transistors connected to an output node, said subset of pull-up transistors processing a first phase displaced clock signal, a second phase displaced clock signal immediately adjacent to said first phase displaced clock signal, and a register bank signal.
Within the receiver's phase-controlled write circuit, comprised of transistor columns driven by phase-shifted clocks (as previously described), each column contains pull-up transistors connected to an output. These pull-up transistors are controlled by a phase-shifted clock, its immediate neighbor, and a signal from a register bank (which may store the buffered signals received by the receiver).
18. The signaling system of claim 17 wherein each transistor column of said set of transistor columns includes a subset of pull-down transistors connected to said output node, said subset of pull-down transistors processing a first phase displaced clock signal, a second phase displaced clock signal immediately adjacent to said first phase displaced clock signal, and a register bank signal.
Within the receiver's phase-controlled write circuit, comprised of transistor columns driven by phase-shifted clocks and containing pull-up transistors (as previously described), each column *also* has pull-down transistors connected to the same output. These pull-down transistors are controlled by a phase-shifted clock, its immediate neighbor, and a signal from a register bank (which may store the buffered signals received by the receiver).
19. The signaling system of claim 11 in combination with a programmable logic device.
This combines the signaling system, comprising a transmitter and receiver using phase-shifted clocks and phase-controlled read/write circuits (as described previously), with a programmable logic device (PLD). This allows the signaling system to be customized or reconfigured for different applications by changing the programming of the PLD.
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December 16, 2014
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