Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method comprising: performing a first error test on a memory, the memory comprising an integrated error correcting code (ECC) portion, wherein the functionality of the ECC portion is bypassed during the first error test; performing a second error test of the memory, wherein the second error test includes testing the functionality of the ECC portion and performing an ECC test upon at least a portion of ECC data; inserting at least one error bit into the ECC data during performance of the second error test; performing the second error test one or more additional times; and shifting the at least one error bit across the ECC data for each of the one or more additional times the second error test is performed.
A method for testing memory with integrated ECC involves two error tests. The first test bypasses the ECC portion to test the raw memory. The second test evaluates the ECC functionality by injecting at least one error bit into the ECC data. This second test is repeated multiple times, shifting the injected error bit across different positions within the ECC data for each repetition. This confirms the ECC is correctly detecting and potentially correcting errors across the ECC data range.
2. The method of claim 1 , further comprising: determining whether an error is present in the memory based at least upon the first error test.
The method of testing memory, including performing a first error test on a memory with an integrated ECC portion where the ECC functionality is bypassed, performing a second error test that includes testing the ECC functionality and testing ECC data, inserting at least one error bit into the ECC data, repeating the second error test, and shifting the error bit across the ECC data, further includes determining if any error exists in the memory based on the first error test results. This initial assessment using the bypassed ECC helps identify fundamental memory cell issues before engaging the ECC testing.
3. The method of claim 2 , further comprising: correcting at least one identified error in the memory in response to determining that an error is present in the memory.
The method of testing memory by performing a first error test bypassing ECC, and then a second error test with ECC enabled and error bit injection with shifting, which includes determining if any error exists in the memory based on the first error test results, further includes automatically correcting any errors detected during the first or second error tests. This allows runtime memory repair based on the ECC's correction capability, ensuring data integrity and continued operation.
4. The method of claim 1 , further comprising: providing a first value for a selection signal to indicate that the functionality of the ECC portion is to be bypassed.
The method of testing memory with integrated ECC, including performing a first error test on a memory with an integrated ECC portion where the ECC functionality is bypassed, performing a second error test that includes testing the ECC functionality and testing ECC data, inserting at least one error bit into the ECC data, repeating the second error test, and shifting the error bit across the ECC data, involves using a selection signal. Setting this signal to a specific (first) value tells the system to disable the ECC functionality during the initial memory test.
5. The method of claim 4 , further comprising: providing a second value for the selection signal to indicate that the error test is to include testing the functionality of the ECC portion.
The method of testing memory with integrated ECC, including performing a first error test on a memory with an integrated ECC portion where the ECC functionality is bypassed, performing a second error test that includes testing the ECC functionality and testing ECC data, inserting at least one error bit into the ECC data, repeating the second error test, and shifting the error bit across the ECC data, involves using a selection signal. Setting the selection signal to a second value indicates that the subsequent error test should include and evaluate the functionality of the integrated ECC.
6. An apparatus, comprising: a memory device; an error correcting code (ECC) circuit communicatively coupled to the memory device; a first switching device communicatively coupled to the memory device and a first portion of the ECC circuit, the first switching device being configured to select at least one of a first input signal or a second input signal; a second switching device communicatively coupled to the memory device and a second portion of the ECC circuit, the second switching device being configured to select at least one of a signal from the memory device or a signal from the second portion of the ECC circuit, wherein the signal from the memory device and the signal from the second portion of the ECC circuit are related to at least one of the first input signal or the second input signal; a first error generating device communicatively coupled to at least one of the memory device or the first switching device, the first error generating device being configured to insert an error into a stream of data; and a third switching device communicatively coupled to the first error generating device, to the memory device and to at least one of the second portion of the ECC circuit or the first switching device, the third switching device being configured to select at least one of an output of the first error generating device and at least one of data from the memory device or an output of the first switching device.
An apparatus for testing memory comprises a memory device, an ECC circuit connected to it, and switching devices. A first switch selects either a first or second input signal and is placed between the memory and a part of the ECC. A second switch chooses either the memory's direct output or the ECC circuit's output (related to the first/second input). An error generator inserts errors into the data stream, and a third switch selects either the error generator's output, direct memory data, or the output of the first switch. This arrangement allows for injecting errors before or after ECC encoding/decoding.
7. The apparatus of claim 6 , wherein the memory device includes a first portion configured to store at least one of read data or write data, and a second portion configured to store ECC data.
The apparatus for testing memory, including a memory device, an ECC circuit, first, second and third switching devices, and a first error generating device, has its memory divided into two portions. The first part stores standard read/write data, while the second part is specifically reserved for storing the ECC data generated by the ECC circuit.
8. The apparatus of claim 6 , wherein the first portion of the ECC circuit is communicatively coupled to an input of the first switching device.
The apparatus for testing memory, including a memory device, an ECC circuit, first, second and third switching devices, and a first error generating device, positions the first portion of the ECC circuit (which might be the encoder) connected to the input of the first switching device. This allows the first switch to select between ECC-encoded or un-encoded data.
9. The apparatus of claim 6 , further comprising: a second error generating device communicatively coupled to a third input signal, the second error generating device being configured to insert an error into a stream of data; and a fourth switching device communicatively coupled to the second error generating device, to the memory device and to the third input signal, the fourth switching device being configured to select at least one of the output of the second error generating device and the third input signal.
This apparatus is designed to test integrated Error Correcting Code (ECC) logic within memory. It comprises a memory device and an ECC circuit connected to it. A first switching device manages signals between the memory and a portion of the ECC circuit, selecting between a first or second input signal. A second switching device routes data, choosing between signals originating from the memory or from a second portion of the ECC circuit. For testing purposes, a first error generating device is included, connected to either the memory or the first switching device, configured to insert errors into a data stream. A third switching device directs these error-laden signals, choosing between the first error generator's output, memory data, or the first switch's output. Additionally, the apparatus features a **second error generating device** that connects to a distinct third input signal and is configured to inject errors into its data stream. A **fourth switching device** is also present, connected to this second error generator, the memory device, and the third input signal. This fourth switch's purpose is to select and pass either the error-inserted data from the second error generator or the original third input signal. ERROR (embedding): Error: Failed to save embedding: Could not find the 'embedding' column of 'patent_claims' in the schema cache
10. The apparatus of claim 9 , wherein the first and second error generating devices each comprise an inverter, and wherein the inserted errors are inverted bits.
This invention relates to error generation in digital systems, specifically for testing or evaluating error detection and correction mechanisms. The apparatus includes a first error generating device and a second error generating device, each configured to introduce errors into a digital signal. The errors are inverted bits, meaning each error is a logical inversion of the original bit value. The first and second error generating devices operate independently, allowing for the insertion of multiple errors at different locations within the signal. This setup enables testing of error detection and correction systems under various error conditions, including scenarios with multiple simultaneous errors. The apparatus may be used in applications such as memory testing, communication systems, or fault-tolerant computing to verify the robustness of error-handling mechanisms. The use of inverters ensures that the errors are simple bit flips, which are common in real-world digital systems due to noise, radiation, or manufacturing defects. The apparatus can be integrated into hardware or software systems to simulate error conditions and evaluate their impact on system performance and reliability.
11. A non-transitory, computer readable storage device encoded with data that, when implemented in a manufacturing facility, configures the manufacturing facility to create an apparatus, where the apparatus comprises: a memory device; an error correcting code (ECC) circuit communicatively coupled to the memory device; a first switching device communicatively coupled to the memory device and a first portion of the ECC circuit, the first switching device being configured to select at least one of a first input signal or a second input signal; a second switching device communicatively coupled to the memory device and a second portion of the ECC circuit, the second switching device being configured to select at least one of a signal from the memory device or a signal from the second portion of the ECC circuit, wherein the signal from the memory device and the signal from the second portion of the ECC circuit are related to at least one of the first input signal or the second input signal; a first error generating device communicatively coupled to at least one of the memory device or the first switching device, the first error generating device being configured to insert an error into a stream of data; and a third switching device communicatively coupled to the first error generating device, to the memory device and to at least one of the second portion of the ECC circuit or the first switching device, the third switching device being configured to select at least one of an output of the first error generating device and at least one of data from the memory device or an output of the first switching device.
A non-transitory, computer readable storage device contains data to configure a manufacturing facility to produce memory testing apparatus. This apparatus includes a memory device, an ECC circuit, a first switching device to select between input signals, a second switching device to select between the memory output or the ECC circuit output, a first error generator to insert errors into data, and a third switching device to select between the error generator's output or memory data or the first switch output.
12. A non-transitory, computer readable storage device, as set forth in claim 11 , encoded with data that, when implemented in a manufacturing facility, configures the manufacturing facility to create an apparatus wherein the memory device includes a first portion configured to store at least one of read data or write data, and a second portion configured to store ECC data.
A non-transitory, computer readable storage device contains data to configure a manufacturing facility to produce memory testing apparatus, which includes a memory device, an ECC circuit, a first switching device to select between input signals, a second switching device to select between the memory output or the ECC circuit output, a first error generator to insert errors into data, and a third switching device to select between the error generator's output or memory data or the first switch output. The memory device is partitioned into a data storage area and an ECC data storage area.
13. A non-transitory, computer readable storage device, as set forth in claim 11 , encoded with data that, when implemented in a manufacturing facility, configures the manufacturing facility to create an apparatus wherein the first portion of the ECC circuit is communicatively coupled to an input of the first switching device.
A non-transitory, computer readable storage device contains data to configure a manufacturing facility to produce memory testing apparatus, which includes a memory device, an ECC circuit, a first switching device to select between input signals, a second switching device to select between the memory output or the ECC circuit output, a first error generator to insert errors into data, and a third switching device to select between the error generator's output or memory data or the first switch output. The ECC circuit's first portion is connected to the input of the first switch.
14. A non-transitory, computer readable storage device, as set forth in claim 11 , encoded with data that, when implemented in a manufacturing facility, configures the manufacturing facility to create an apparatus, where the apparatus further comprises: a second error generating device communicatively coupled to a third input signal, the second error generating device being configured to insert an error into a stream of data; and a fourth switching device communicatively coupled to the second error generating device, to the memory device and to the third input signal, the fourth switching device being configured to select at least one of the output of the second error generating device and the third input signal.
A non-transitory, computer readable storage device contains data to configure a manufacturing facility to produce memory testing apparatus, which includes a memory device, an ECC circuit, a first switching device to select between input signals, a second switching device to select between the memory output or the ECC circuit output, a first error generator to insert errors into data, and a third switching device to select between the error generator's output or memory data or the first switch output. The apparatus also includes a second error generator to inject errors into a third input signal and a fourth switch to select the output of this error generator or the third input signal.
15. A non-transitory, computer readable storage device, as set forth in claim 14 , encoded with data that, when implemented in a manufacturing facility, configures the manufacturing facility to create an apparatus, wherein the first and second error generating devices each comprise an inverter, and wherein the inserted errors are inverted bits.
A non-transitory, computer readable storage device contains data to configure a manufacturing facility to produce memory testing apparatus, which includes a memory device, an ECC circuit, first, second, third and fourth switching devices, and first and second error generating devices. The first and second error generators are inverters used to flip bits, creating controlled errors for memory testing.
16. A non-transitory, computer readable program storage device encoded with instructions that, when executed by a processing device, perform a method, where the method comprises: performing a first error test on a memory, the memory comprising an integrated error correcting code (ECC) portion, wherein the functionality of the ECC portion is bypassed during the first error test; performing a second error test of the memory, wherein the second error test includes testing the functionality of the ECC portion and performing an ECC test upon at least a portion of ECC data; inserting at least one error bit into the ECC data during the performance of the second error test; performing the second error test one or more additional times; and shifting the at least one error bit across the ECC data for each of the one or more additional times the second error test is performed.
A computer program performs a method for testing memory with integrated ECC by first performing an error test with the ECC bypassed. Then it performs a second error test that includes testing the ECC functionality on ECC data, inserting an error bit into the ECC data during this second test. The second error test is repeated one or more times with the error bit shifted in the ECC data for each iteration.
17. The non-transitory, computer readable program storage device encoded with instructions that, when executed by a processing device, performs the method of claim 16 , further comprising: determining whether an error is present in the memory based at least upon the first error test.
The computer program performing a method of first testing memory with integrated ECC by first performing an error test with the ECC bypassed, then a second error test with ECC enabled that includes testing the ECC functionality on ECC data, inserting an error bit into the ECC data during the second test, repeating the second error test, and shifting the injected error bit across the ECC data for each repetition, also includes determining whether an error is present in the memory based on the results of the first error test (where the ECC was bypassed).
18. The non-transitory, computer readable program storage device encoded with instructions that, when executed by a processing device, performs the method of claim 17 , further comprising: correcting at least one identified error in the memory in response to determining that an error is present in the memory.
The computer program performing a method of testing memory with integrated ECC by first performing an error test with the ECC bypassed, then a second error test with ECC enabled that includes testing the ECC functionality on ECC data, inserting an error bit into the ECC data during the second test, repeating the second error test, and shifting the injected error bit across the ECC data for each repetition, and determining if any error exists in the memory based on the ECC bypassed first test, further involves automatically correcting identified errors in the memory in response to determining an error exists.
19. The non-transitory, computer readable program storage device encoded with instructions that, when executed by a processing device, performs the method of claim 16 , further comprising: providing a first value for a selection signal to indicate that the functionality of the ECC portion is to be bypassed.
The computer program performing a method of testing memory with integrated ECC by first performing an error test with the ECC bypassed, then a second error test with ECC enabled that includes testing the ECC functionality on ECC data, inserting an error bit into the ECC data during the second test, repeating the second error test, and shifting the injected error bit across the ECC data for each repetition, involves setting a selection signal to a specific value in order to bypass the ECC during the initial error test.
20. The non-transitory, computer readable program storage device encoded with instructions that, when executed by a processing device, performs the method of claim 19 , further comprising: providing a second value for a selection signal to indicate that the error test is to include testing the functionality of the ECC portion.
The computer program performing a method of testing memory with integrated ECC by first performing an error test with the ECC bypassed, then a second error test with ECC enabled that includes testing the ECC functionality on ECC data, inserting an error bit into the ECC data during the second test, repeating the second error test, and shifting the injected error bit across the ECC data for each repetition, involves setting a selection signal to another value to indicate that the second error test should include testing the functionality of the integrated ECC circuit.
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December 16, 2014
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