Multi-Port Memory and Operation

1. An electronic system, comprising: a controller; and a memory, the memory comprising: two or more ports, each port comprising one or more regions of memory and control circuitry coupled to the one or more regions of memory; and an interport control bus for communicating commands between the control circuitry of each of the two or more ports; wherein different ones of two or more control busses are respectively coupled to the two or more ports and to the controller, the two or more control busses being different than the interport control bus; wherein the control circuitry of each of the two or more ports is configured to select whether to respond to commands received from either the controller over the one control bus coupled to that port or the interport control bus.

2. The electronic system of claim 1 , wherein the control circuitry of each of the ports is configured to selectively pass a command received from the one control bus coupled to that port and the controller to the interport control bus.

3. The electronic system of claim 1 , wherein at least one of the two or more ports is configured to selectively isolate itself from the interport control bus.

4. The electronic system of claim 1 , further comprising two or more data buses coupled to the controller and respectively coupled to the two or more ports.

5. An electronic system, comprising: a controller; and a memory, the memory comprising: a first port comprising a memory region and control circuitry coupled to the memory region; a first control bus coupled between the controller and the control circuitry of the first port; a second port comprising a memory region and control circuitry coupled to the memory region; a second control bus coupled between the controller and the control circuitry of the second port, the second control bus different than the first control bus; and an interport control bus, different than the first and second control busses, for communicating commands between the control circuitry of the first and second ports; wherein the control circuitry of the first port is configured to select whether to respond to commands received from either the controller over the first control bus or the interport control bus; and wherein the control circuitry of the second port is configured to select whether to respond to commands received from either the controller over the second control bus or the interport control bus.

6. The electronic system of claim 5 , wherein the first and second control busses each comprise one or more lanes for receiving commands and addresses either in serial or parallel fashion.

7. The electronic system of claim 5 , further comprising a first data bus coupled between the memory region of the first port and the controller, and a second data bus coupled between the memory region of the second port and the controller.

8. The electronic system of claim 7 , wherein the first and second data buses each comprise one or more lanes for sending or receiving data either in serial or parallel fashion.

9. The electronic system of claim 7 , wherein data is conveyed between controller and the memory region of the first port over the first data bus without passing through the control circuitry of the first port, and wherein data is conveyed between controller and the memory region of the second port over the second data bus without passing through the control circuitry of the second port.

10. The electronic system of claim 5 , further comprising: a third port comprising control circuitry coupled to a memory region of the third port; and a third control bus coupled between the controller and the control circuitry of the third port; wherein the control circuitry of the third port is not coupled to an interport control bus.

11. The electronic system of claim 5 wherein the control circuitry of each of the first and second ports is configured to selectively isolate itself from the interport control bus.

12. The electronic system of claim 5 , wherein the control circuitry of the first port is configured to selectively pass a command received from the controller over the first control bus to the interport control bus, and wherein the control circuitry of the second port is configured to selectively pass a command received from the controller over the second control bus to the interport control bus.

13. The electronic system of claim 5 , wherein the control circuitry of the first port is hard programmed to respond to commands received from either the controller over the first control bus or the interport control bus, and wherein the control circuitry of the second port is hard programmed to respond to commands received from either the controller over the second control bus or the interport control bus.

14. The electronic system of claim 13 , wherein the control circuitry of each of the first and second ports is hard programmed using a control mechanism selected from the group consisting of fuses, anti-fuses, bond wire option and manufacturing metal layer.

15. The electronic system of claim 5 , wherein the control circuitry of the first port is dynamically configured to select whether to respond to commands received from either the controller over the first control bus or the interport control bus, and wherein the control circuitry of the second port is dynamically configured to select whether to respond to commands received from either the controller over the second control bus or the interport control bus.

16. An electronic system, comprising: a controller; and a memory, the memory comprising: two or more ports, each port comprising a memory region and control circuitry for controlling access to the memory region in response to commands; and at least one interport control bus for communicating commands between the control circuitry of the two of more of the ports; wherein the control circuitry of at least one of the ports is configured to selectively respond to commands received from either a control bus coupled between the controller and the at least one of the ports or the at least one interport control bus; and wherein less than all of the ports are coupled to an interport control bus.

17. The electronic system of claim 16 , wherein the memory region of each of the two or more ports comprises banks of memory cells selected from the group consisting of volatile and non-volatile memory cells.

18. The electronic system of claim 16 , further comprising a plurality of data buses coupled to the controller, wherein respective ones of the plurality of data buses are respectively coupled to the memory region of each of the two or more ports.

19. The electronic system of claim 16 , wherein the control circuitry of a port not coupled to an interport control bus is coupled to the controller by a control bus.

20. An electronic system, comprising: a controller; and a memory, the memory comprising: two or more ports, each port comprising one or more regions of memory and control circuitry for controlling access to the one or more regions of memory in response to commands; and an interport control bus for communicating commands between the control circuitry of each of the two or more ports; wherein at least one of the two or more ports is configured to selectively isolate itself from the interport control bus; and wherein the control circuitry of each of the two or more ports is configured to selectively respond to commands received from either the controller or the interport control bus.

21. The electronic system of claim 20 , wherein the at least one of the two or more ports being configured to selectively isolate itself from the interport control bus comprises the control circuitry of the at least one of the two or more ports being configured to selectively isolate the control circuitry of the at least one of the two or more ports from the interport control bus.

22. The electronic system of claim 20 , wherein the at least one of the two or more ports being configured to selectively isolate itself from the interport control bus comprises the at least one of the two or more ports comprising a switch configured to selectively isolate the at least one of the two or more ports from the interport control bus.