Power Supply Circuit Employed in Computer for Performing Different Standby Modes

1. A power supply circuit employed in a computer, comprising: a basic input output system (BIOS) configured for storing different operation modes of the computer; a super input output (SIO) configured for generating standby mode signals according to the different operation modes; a bivibrator configured for generating a reference signal when upon receiving a clock signal from the computer when the computer is turned on; a logical selector configured for generating a standby control signal in response to the reference signal and one of the standby mode signals; and a voltage converter configured for transforming the first standby voltage into a second standby voltage to drive the SIO in response to the standby control signal, wherein the SIO receives the second standby voltage before the clock signal is delayed and provided to the SIO to turn on the computer.

2. The power supply circuit of claim 1 , further comprising a delay circuit configured for delaying the clock signal.

3. The power supply circuit of claim 2 , wherein the delay circuit comprises a first resistor, a first Schmitt trigger, and a second Schmitt trigger connected in series in that order, the delay circuit further comprises a first capacitor connected between an input of the first Schmitt trigger and ground.

4. The power supply circuit of claim 3 , further comprising a clock input connected in series to the delay circuit via a forward biased first diode, the clock input is also connected in series to the bivibrator via a forward biased second diode.

5. The power supply circuit of claim 4 , wherein the bivibrator generates a first voltage as the reference voltage when the bivibrator receives the clock signal, and generates the second voltage as the reference voltage when the bivibrator does not receive the clock signal, wherein the first voltage and second voltage correspond to logic 1 and logic 0 respectively.

6. The power supply circuit of claim 4 , wherein the bivibrator comprises a third diode, a fourth diode, first to fourth capacitors, a first transistor, a second transistor, and second to sixth resistors, collectors of the first and the second transistors are connected to the first standby voltage, emitters of the first and the second transistors are grounded, the second resistor, the third resistor, the forward biased fourth diode and the sixth resistor are connected in series between the first standby voltage and ground, the third capacitor is connected in parallel with the third resistor, base of the second transistor is connected to the anode of the fourth diode, the fourth resistor, the fifth resistor, the forward biased third diode, and the sixth resistor is connected between the first standby voltage and ground, the fourth capacitor is connected in parallel with the fifth resistor, base of the first transistor is connected to the anode of the third diode, the cathodes of the third and the fourth diodes are connected to the cathode of the second diode via the second capacitor, the collector of the second transistor is configured to output the reference voltage.

7. The power supply circuit of claim 6 , wherein the first and the second transistors are npn bipolar junction transistors.

8. The power supply circuit of claim 6 , wherein the logical selector comprises an OR gate and a detector, the OR gate comprises a first logic input configured for receiving the reference signal, a second logic input configured for receiving the standby mode signals, and a logic output configured for outputting the standby control signal to the voltage converter via the detector.

9. The power supply circuit of claim 8 , wherein the detector is a fusion controller hub (FCH).

10. The power supply circuit of claim 8 , wherein the voltage converter is a DC to DC chip and comprises an enable pin configured for receiving the standby control signal, a voltage input configured for receiving the first standby voltage, a voltage output configured for outputting the second standby voltage.

11. The power supply circuit of claim 9 , wherein the voltage converter further comprises initial pin, a ground pin, a seventh resistor and an eighth resistor, the initial pin is grounded via the seventh resistor, and the eight resistor is connected between the between the voltage output and the initial pin.

12. The power supply circuit of claim 11 , further comprising a reset circuit configured to pull down the reference voltage from the first voltage into the second voltage when the computer normally works, wherein the first voltage and second voltage correspond to logic 1 and logic 0 respectively.

13. The power supply circuit of claim 11 , wherein the reset circuit comprises a third transistor and a ninth resistor, collector of the third transistor is connected to the first input of the logical selector, emitter of the third transistor is grounded, base of the third transistor configured for receiving an enable signal.

14. The power supply circuit of claim 1 , wherein the operation modes of the computer comprises a normal work mode, a normal standby mode, a super standby mode, and an auto standby mode.

15. The power supply circuit of claim 14 , wherein the standby mode signals comprises a normal standby signal, a super standby signal, and an auto standby signal, the SIO generates the normal standby signal when the computer enters the normal standby mode, the SIO generates the super standby signal when the computer enters the super standby mode, and the SIO generates the auto standby signal when the computer enters the auto standby mode.

16. The power supply circuit of claim 15 , wherein voltage converter generates the second standby voltage in response to the normal standby signal when the computer enters the normal standby mode.

17. The power supply circuit of claim 15 , wherein voltage converter stops generating the second standby voltage in response to the super standby signal when the computer enters the super standby mode.

18. The power supply circuit of claim 15 , wherein voltage converter generates the second standby voltage in a predetermined time and stops generating the second standby voltage after the predetermined time is passed when the computer enters the auto standby mode, in response to the auto standby signal.

19. The power supply circuit of claim 18 , the predetermined time is selected from the group consisting of thirty seconds, two minutes, and five minutes.