Multi-Stage Command Processing Pipeline and Method for Shared Cache Access

1. A command processing pipeline configured to be coupled to a shared cache, the command processing pipeline comprising: a first command processing stage configured to perform a comparison, in a first clock cycle, of an address associated with a first cache command to addresses stored in the cache; a second command processing stage configured to, in a second clock cycle, (i) receive the first cache command from the first command processing stage, and (ii) based on a result of the comparison, process the first cache command by one or more of (A) providing a read access to one or both of a data memory and an error correcting code memory included in the cache, (B) providing a write access to one or both of the data memory and the error correcting code memory included in the cache, and (C) generating an error correcting code associated with data to be written to the data memory; and a third command processing stage configured to, in a third clock cycle, (i) receive the first cache command from the second command processing stage, and (ii) process the first cache command by writing data associated with the first cache command to one of a valid memory and a dirty memory included in the cache, the valid memory and the dirty memory being different from the data memory.

2. The command processing pipeline of claim 1 , further comprising: a fourth command processing stage configured to, in a fourth clock cycle, (i) receive the first cache command from the third command processing stage, and (ii) perform an error correcting code calculation on data read from the data memory.

3. The command processing pipeline of claim 2 , further comprising: a fifth command processing stage configured to, in a fifth clock cycle, (i) receive the first cache command from the fourth command processing stage, and (ii) perform an error correcting code correction on data read from the data memory.

4. The command processing pipeline of claim 1 , wherein the first command processing stage is further configured to: irrespective of a result of the comparison, receive, in the second clock cycle, a second cache command.

5. The command processing pipeline of claim 1 , wherein: the first command processing stage is further configured to perform the comparison by comparing the address associated with the first cache command with addresses stored in one or more of a tag memory, the dirty memory, and the valid memory included in the cache.

6. The command processing pipeline of claim 5 , wherein the result of the comparison indicates whether the first cache command is a hit or a miss, and wherein the result of the comparison is determined based at least in part on comparing the address associated with the first cache command with addresses stored in one or more of the tag memory, the dirty memory, and the valid memory included in the cache.

7. The command processing pipeline of claim 1 , wherein the first command processing stage, the second command processing stage and the third command processing stage are three consecutive command processing stages of the command processing pipeline.

8. The command processing pipeline of claim 1 , wherein each of the command processing stages of the command processing pipeline has corresponding one or two adjacent command processing stages, the command processing stages of the command processing pipeline further configured to: access a plurality of cache resources while processing the first cache command, such that each of the command processing stages accesses cache resources that are different from cache resources accessed by the corresponding one or two adjacent command processing stages.

9. The command processing pipeline of claim 1 , wherein: the first command processing stage is configured to perform the comparison based on accessing a first group of cache resources; and the second command processing stage is configured to process the first cache command based on accessing a second group of cache resources that is different from the first group of cache resources.

10. The command processing pipeline of claim 9 , wherein: the first group of cache resources comprises one or more of a tag memory, the dirty memory, and the valid memory; and the second group of cache resources comprises one or more of the data memory and the error correcting code memory.

11. The command processing pipeline of claim 10 , wherein: the tag memory is configured to store addresses of data currently stored in the data memory; the dirty memory is configured to store one or both of (i) addresses of data in the data memory that has been recently modified, and (ii) addresses of data in the data memory that are not currently in synchronization with a main memory coupled to the cache; the valid memory is configured to store addresses of data in the data memory that are valid; and the error correcting code memory is configured to store error correcting codes associated with data stored in the data memory.

12. The command processing pipeline of claim 1 , wherein: the first command processing stage is further configured to, in the second clock cycle, (i) receive a line fill update command to write data in a pre-allocated entry in the cache, in response to a cache miss of a previously issued cache command, and (ii) perform a look-up of an address associated with the line fill update command in the cache; and the second command processing stage is further configured to, in the third clock cycle, (i) receive the line fill update command from the first command processing stage, and (ii) provide a write access to each of the data memory and the error correcting code memory included in the cache.

13. A method for accessing a shared cache using a command processing pipeline, the method comprising: receiving, by a first command processing stage and in a first clock cycle, a first cache command; performing a comparison, at the first command processing stage and in the first clock cycle, of an address associated with the first cache command to addresses stored in the cache; receiving, by a second command processing stage and in a second clock cycle, the first cache command from the first command processing stage; based on a result of the comparison, processing, by the second command processing stage and in the second clock cycle, the first cache command by one or more of (A) providing a read access to one or both of a data memory and an error correcting code memory included in the cache, (B) providing a write access to one or both of the data memory and the error correcting code memory included in the cache, and (C) generating an error correcting code associated with data to be written to the data memory; receiving, by a third command processing stage and in a third clock cycle, the first cache command from the second command processing stage; and processing, by the third command processing stage and in the third clock cycle, the first cache command by writing data associated with the first cache command to one of a valid memory and a dirty memory included in the cache, the valid memory and the dirty memory being different from the data memory.

14. The method of claim 13 , further comprising: receiving, by a fourth command processing stage and in a fourth clock cycle, the first cache command from the third command processing stage; and performing, by the fourth command processing stage and in the fourth clock cycle, an error correcting code calculation on data read from the data memory.

15. The method of claim 14 , further comprising: receiving, by a fifth command processing stage and in a fifth clock cycle, the first cache command from the fourth command processing stage; and performing, by the fifth command processing stage and in the fifth clock cycle, an error correcting code correction on data read from the data memory.

16. The method of claim 13 , further comprising: irrespective of a result of the comparison, receiving, at the first command processing stage and in the second clock cycle, a second cache command.

17. The method of claim 13 , wherein performing the comparison at the first command processing stage further comprises: performing the comparison, by comparing the address associated with the first cache command with addresses stored in one or more of a tag memory, the dirty memory, and the valid memory included in the cache.

18. The method of claim 17 , further comprising: determining the result of the comparison by determining whether the first cache command is a hit or a miss, based at least in part on comparing the address associated with the first cache command with addresses stored in one or more of the tag memory, the dirty memory, and the valid memory included in the cache.

19. The method of claim 13 , wherein each of the command processing stages of the command processing pipeline has corresponding one or two adjacent command processing stages, the method further comprising: accessing a plurality of cache resources while processing the first cache command, such that each of the command processing stages accesses cache resources that are different from cache resources accessed by the corresponding one or two adjacent command processing stages.

20. The method of claim 13 , wherein: performing the comparison, at the first command processing stage and in the first clock cycle, comprises performing the comparison, by accessing a first group of cache resources; and processing, by the second command processing stage and in the second clock cycle, the first cache command comprises processing the first cache command by accessing a second group of cache resources that is different from the first group of cache resources.

21. The method of claim 13 , further comprising: receiving, by the first command processing stage and in the second clock cycle, a line fill update command to write data in a pre-allocated entry in the cache, in response to a cache miss of a previously issued cache command; performing, by the first command processing stage and in the second clock cycle, a look-up of an address associated with the line fill update command in the cache; receiving, by the second command processing stage and in the third clock cycle, the line fill update command from the first command processing stage; and providing, by the second command processing stage and in the third clock cycle, a write access to each of the data memory and the error correcting code memory included in the cache.