Spike Domain Neuron Circuit with Programmable Kinetic Dynamic, Homeostatic Plasticity and Axonal Delays

1. A spike domain asynchronous neuron circuit comprising: a first spike to exponential circuit for emulating kinetic dynamics at a neuron input and converting voltage spikes into exponentials, the first spike to exponential circuit having a first plurality of voltage-type spike domain inputs and having a first voltage-type spike exponential output; a first adjustable gain circuit for emulating homeostatic plasticity coupled to the first voltage-type spike exponential output and having a first current output; a neuron core circuit coupled to the first current output for emulating a neuron core and having a spike encoded voltage output; a filter and comparator circuit coupled to the spike encoded voltage output and having a gain control output coupled to the first adjustable gain circuit for controlling a gain of the first adjustable gain circuit; and an adjustable delay circuit for emulating an axonal delay coupled to the spike encoded voltage output and having an axonal delay output.

2. The circuit of claim 1 further comprising: a second spike to exponential circuit for emulating kinetic dynamics at a neuron input and converting voltage spikes into exponentials, the second spike to exponential circuit having a second plurality of voltage-type spike domain inputs and having a second voltage-type spike exponential output; and a second adjustable gain circuit for emulating homeostatic plasticity coupled to the second voltage-type spike exponential output and having a second current output; wherein the gain control output is coupled to the second adjustable gain circuit for controlling the gain of the second adjustable gain circuit; wherein the first current output is added to the second current output to form a summed current output; and wherein the neuron core is coupled to the summed current output.

3. The circuit of claim 2 further comprising: a first time constant control coupled to the first spike to exponential circuit for adjusting the kinetic dynamics of the first spike to exponential circuit; a second time constant control coupled to the second spike to exponential circuit for adjusting the kinetic dynamics of the second spike to exponential circuit; a neuron spike rate control coupled to the filter and comparator circuit for setting a target neuron spike rate; and a delay control coupled to the adjustable delay circuit for setting a target axonal delay.

4. The circuit of claim 2 wherein: the first voltage-type spike exponential output and the second voltage-type spike exponential output each have voltage signals that spike to a high level and then exponentially decrease to a low level.

5. The circuit of claim 1 wherein: the axonal delay output comprises a voltage-type spike domain signal alternating between a high and a low amplitude value; wherein information in the voltage-type spike domain signal is encoded in timing of the signal.

6. The circuit of claim 2 wherein the first spike to exponential circuit and the second spike to exponential circuit each comprise: a plurality of amplifiers, each amplifier coupled to one of the plurality of respective first or second voltage-type spike domain inputs; and an integrator coupled to an output of each amplifier.

7. The circuit of claim 6 wherein the integrator comprises an integrator having a negative feedback having variable gain controlled by a respective first or second time constant control.

8. The circuit of claim 6 wherein the integrator comprises: a capacitor; and a variable resistor controlled by a respective first or second time constant control.

9. The circuit of claim 2 wherein: the first adjustable gain circuit comprises a first transconductance amplifier having a gain controlled by the gain control output; and the second adjustable gain circuit comprises a second transconductance amplifier having a gain controlled by the gain control output.

10. The circuit of claim 2 wherein the filter and comparator circuit comprises: a low pass filter coupled to the spike encoded voltage output of the neuron core circuit; and a comparator with one input coupled to the low pass filter and another input coupled to a neuron spike rate control for setting a target neuron spike rate; wherein the comparator output is the gain control output coupled to the first adjustable gain circuit for controlling the gain of the first adjustable gain circuit and coupled to the second adjustable gain circuit for controlling the gain of the second adjustable gain circuit.

11. The circuit of claim 2 wherein the neuron core circuit comprises: a voltage controlled current source; a capacitor; and a hysteresis comparator, wherein an input to the hysteresis comparator, an output of the voltage controlled current source, and the capacitor are coupled to the summed current output; and wherein the voltage controlled current source is controlled by an output of the hysteresis comparator.

12. The circuit of claim 11 wherein the hysteresis comparator comprises: a nonlinear transconductance amplifier with positive feedback; and a resistor.

13. The circuit of claim 12 wherein the voltage controlled current source comprises: a first transistor coupled to a voltage source; a second transistor coupled to the first transistor; and an inverter coupled to an output of the transconductance amplifier and to the second transistor.

14. The circuit of claim 1 wherein the neuron core circuit comprises: a capacitor; a resistor in parallel with the capacitor; a switch; and a comparator having a positive input connected to the capacitor, the resistor, and the switch, having a negative input connected to a V th voltage, and having an output; wherein the output controls the switch to either be open or to close to connect the positive input of the comparator to a V reset voltage; and wherein when the capacitor is charged above V th the output controls the switch to close thereby discharging the capacitor, whereupon the output controls the switch to open, thereby repeating the process.

15. The circuit of claim 1 wherein the neuron core circuit is an integrate and fire neuron and implements the equation C ⁢ ⅆ v m ⅆ t = i - v m R + V B R .

16. The circuit of claim 1 wherein the adjustable delay circuit comprises: a plurality of delay stages connected in series; a selector having the axonal delay output; a control coupled to the selector; wherein the control selects between the axonal delay output, or an output of any one of the plurality of delay stages.

17. The circuit of claim 16 wherein a delay stage comprises: a flip flop; a transconductance amplifier coupled to the flip flop; a capacitor coupled to the transconductance amplifier; a comparator coupled to the capacitor and a reference voltage; and a switch; wherein when a voltage on the capacitor reaches the reference voltage the switch is closed and the capacitor is discharged and the flip flop is reset to again let an input voltage charge the capacitor and the switch is opened.

18. The circuit of claim 1 wherein the adjustable delay circuit comprises: a differential circuit comprising two flip-flops, two amplifiers, two capacitors and one differential comparator.

19. A method of providing a spike domain asynchronous neuron circuit comprising: forming a first spike to exponential circuit for emulating kinetic dynamics at a neuron input and converting voltage spikes into exponentials, the first spike to exponential circuit having a first plurality of voltage-type spike domain inputs and having a first voltage-type spike exponential output; forming a first adjustable gain circuit for emulating homeostatic plasticity coupled to the first voltage-type spike exponential output and having a first current output; forming a neuron core circuit coupled to the first current output for emulating a neuron core and having a spike encoded voltage output; forming a filter and comparator circuit coupled to the spike encoded voltage output and having a gain control output coupled to the first adjustable gain circuit for controlling a gain of the first adjustable gain circuit; and forming an adjustable delay circuit for emulating an axonal delay coupled to the spike encoded voltage output and having an axonal delay output.

20. The method of claim 19 further comprising: forming a second spike to exponential circuit for emulating kinetic dynamics at a neuron input and converting voltage spikes into exponentials, the second spike to exponential circuit having a second plurality of voltage-type spike domain inputs and having a second voltage-type spike exponential output; and forming a second adjustable gain circuit for emulating homeostatic plasticity coupled to the second voltage-type spike exponential output and having a second current output; wherein the gain control output is coupled to the second adjustable gain circuit for controlling the gain of the second adjustable gain circuit; wherein the first current output is added to the second current output to form a summed current output; and wherein the neuron core is coupled to the summed current output.

21. The method of claim 20 further comprising: providing a first time constant control coupled to the first spike to exponential circuit for adjusting the kinetic dynamics of the first spike to exponential circuit; providing a second time constant control coupled to the second spike to exponential circuit for adjusting the kinetic dynamics of the second spike to exponential circuit; providing a neuron spike rate control coupled to the filter and comparator circuit for setting a target neuron spike rate; and providing a delay control coupled to the adjustable delay circuit for setting a target axonal delay.

22. The method of claim 20 wherein: the first voltage-type spike exponential output and the second voltage-type spike exponential output each have voltage signals that spike to a high level and then exponentially decrease to a low level.

23. The method of claim 19 wherein: the axonal delay output comprises a voltage-type spike domain signal alternating between a high and a low amplitude value; wherein information in the voltage-type spike domain signal is encoded in timing of the signal.