Integrated Link Calibration and Multi-Processor Topology Discovery

1. A method comprising: establishing a first of a plurality of processors in a multi-processor system as a director of integrated interconnect calibration and dynamic topology discovery, wherein a plurality of high speed interconnects connects the plurality of processors with each other; calibrating each of the plurality of high speed interconnects as directed by the director via a shared hardware resource, wherein the shared hardware resource is shared among the plurality of processors; and incrementally discovering topology of the multi-processor system as each of the plurality of high speed interconnects is calibrated and based, at least in part, on results of the plurality of high speed interconnects being calibrated.

2. The method of claim 1 further comprising initializing, by the director, the shared hardware resource with at least one data structure to host indications of the plurality of processors, indications of the topology of the multi-processor system, results of said calibrating each of the plurality of high speed interconnects, and indications of tasks dispatched by the director for directing said calibrating each of the plurality of high speed interconnects.

3. The method of claim 2 , wherein said initializing the shared hardware resource further comprises recording an identifier of the first processor to indicate that the first processor has been established as the director.

4. The method of claim 1 further comprising the other ones of the plurality of processors writing their identifiers into the shared hardware resource.

5. The method of claim 1 , wherein said calibrating each of the plurality of high speed interconnects as directed by the director via the shared hardware resources comprises: the director writing a calibration task indication into the shared hardware resource for a second of the plurality of processors; the second of the plurality of processors reading the calibration task indication; and the second of the plurality of processors initiating calibration of a first of the plurality of high speed interconnects, which is coupled to the second of the plurality of processors, responsive to said reading the calibration task indication.

6. The method of claim 5 further comprising: the director determining that the second of the plurality of processors has successfully initiated the calibration of the first high speed interconnect; the director writing into the shared hardware resource a plurality of receive calibration task indications for uncalibrated ones of the plurality of high speed interconnects of other ones of the plurality of processors responsive to said determining that the second of the plurality of processors has successfully initiated the calibration of the first high speed interconnect; the other ones of the plurality of processors, which are not the first and the second of the plurality of processors, reading the plurality of receive calibration task indications; and the other ones of the plurality of processors initiating receive calibration on the uncalibrated ones of the plurality of high speed interconnects responsive to said reading the plurality of receive calibration task indications.

7. The method of claim 1 , wherein said incrementally discovering topology of the multi-processor system as each of the plurality of high speed interconnects is calibrated based on the result of each of the plurality of high speed interconnects being calibrated comprises: recording an indication of the result for each attempted calibration of the plurality of high speed interconnects, wherein each of the indications corresponding to a successfully calibrated one of the plurality of high speed interconnects indicates the processors of the plurality of processors connected by the successfully calibrated high speed interconnect.

8. A method for integrated high speed interconnect calibration and topology discovery in a multi-processor system, wherein processors of the multi-processor system are connected by a plurality of high speed interconnects, the method comprising: coordinating calibration of each of the plurality of high speed interconnects as directed by a first of the processors via a shared hardware resource, wherein the shared hardware resource is shared among the processors; writing a result of attempted calibration of each of the plurality of high speed interconnects into the shared hardware resource; and for each successfully calibrated one of the plurality of high speed interconnects, using the corresponding result as information about topology of the multi-processor system.

9. The method of claim 8 further comprising establishing the first of the processors as a director, wherein the director writes tasks into the shared hardware resource and reads results in the shared hardware resource for said coordinating the calibration of each of the plurality of high speed interconnects.