Techniques For Transferring Time Information Between Clock Domains

1. A circuit comprising: a logic circuit to generate a digital value in response to a first periodic signal; a first storage circuit to store time information in response to a second periodic signal; a second storage circuit to store the digital value in response to the second periodic signal; a timing detection circuit comprising a first shift register, the timing detection circuit to generate a detection signal indicating a timing difference between the first periodic signal and the second periodic signal based on the digital value stored in the second storage circuit and based on values stored in the first shift register; and a compensation circuit to generate adjusted time information based on the time information stored in the first storage circuit and the detection signal.

2. The circuit of claim 1 , wherein the logic circuit comprises: a first counter circuit to generate first count signals having a binary value in response to the first periodic signal; and a binary-to-Gray code converter circuit to convert the binary value of the first count signals to second count signals having a Gray coded value in response to the first periodic signal, wherein the second storage circuit stores the Gray coded value of the second count signals in response to the second periodic signal.

3. The circuit of claim 1 , wherein the second storage circuit is a second shift register, and wherein the second shift register is coupled to the first shift register.

4. The circuit of claim 3 , wherein the timing detection circuit comprises XOR gate circuits, wherein each of the XOR gate circuits generates an XOR signal based on a subset of the values stored in the first shift register, and wherein the timing detection circuit generates the detection signal based on two of the XOR signals having the same logic state.

5. The circuit of claim 1 , wherein the timing detection circuit comprises a counter circuit to generate count signals in response to the second periodic signal, and wherein the timing detection circuit generates the detection signal based on the count signals.

6. The circuit of claim 1 , wherein the logic circuit comprises: a toggling bit generator circuit to toggle a digital signal in response to the first periodic signal, wherein the second storage circuit stores the digital value of the digital signal in response to the second periodic signal.

7. The circuit of claim 1 , wherein the timing detection circuit further comprises a calculation circuit to generate the detection signal based on two signals stored in adjacent flip-flops in the first shift register having a same value.

8. The circuit of claim 1 , wherein the adjusted time information is provided to a transmitter for transmission via a communications link.

9. A circuit comprising: a logic circuit to generate a digital value in response to a first periodic signal; a first storage circuit to store time information in response to a second periodic signal, wherein the first storage circuit stores the digital value; a second storage circuit to store the digital value in response to the second periodic signal; a timing detection circuit to generate a detection signal indicating a timing difference between the first periodic signal and the second periodic signal based on the digital value stored in the first storage circuit and the digital value stored in the second storage circuit; and a compensation circuit to generate adjusted time information based on the time information stored in the first storage circuit and the detection signal.

10. A circuit comprising: a logic circuit to generate a digital value in response to a first periodic signal; an asynchronous first-in-first-out buffer circuit to store time information and the digital value in response to the first periodic signal, and to output the time information and the digital value in response to a second periodic signal; a storage circuit to store the digital value in response to the second periodic signal; a timing detection circuit to generate a detection signal indicating a timing difference between the first periodic signal and the second periodic signal based on the digital value stored in the storage circuit; and a compensation circuit to generate adjusted time information based on the time information stored in the asynchronous first-in-first-out buffer circuit and the detection signal.

11. The circuit of claim 10 , wherein the timing detection circuit generates the detection signal based on the digital value stored in the asynchronous first-in-first-out buffer circuit and the digital value stored in the storage circuit.

12. A circuit comprising: a logic circuit that generates a digital signal in response to a first timing signal; a first storage circuit that stores time information and a value of the digital signal in response to a second timing signal; a second storage circuit that stores a value of the digital signal in response to the second timing signal; a detection circuit that generates a detection signal based on the value of the digital signal stored in the second storage circuit; a calculation circuit that calculates an offset signal indicating a timing difference between the first timing signal and the second timing signal based on the detection signal and based on the value of the digital signal stored in the first storage circuit; and an adjustment circuit that generates adjusted time information based on the time information stored in the first storage circuit and based on the offset signal, wherein the first timing signal and the second timing signal have different frequencies.

13. The circuit of claim 12 , wherein the logic circuit comprises: a first counter circuit to generate first count signals having a binary value in response to the first timing signal; and a binary-to-Gray code converter circuit to convert the binary value of the first count signals to second count signals having a Gray coded value in response to the first timing signal, wherein the second storage circuit stores the Gray coded value of the second count signals in response to the second timing signal.

14. The circuit of claim 12 , wherein the detection circuit comprises a shift register to store values based on the value of the digital signal stored in the second storage circuit, and wherein the detection circuit generates the detection signal based on at least one of the values stored in the shift register.

15. The circuit of claim 12 , wherein the detection circuit comprises a counter circuit to generate count signals, and wherein the counter circuit resets the count signals in response to an output signal of the second storage circuit.

16. The circuit of claim 12 , wherein the logic circuit comprises: a toggling bit generator circuit to toggle the digital signal between first and second logic states in response to the first timing signal.

17. The circuit of claim 12 , wherein the detection circuit comprises a shift register to store register values, wherein each of the register values is based on the digital signal at a different time, and wherein the calculation circuit generates the offset signal based on two register values stored in adjacent flip-flops in the shift register having a same value.

18. A method comprising: generating a digital signal in response to a first timing signal; storing time information and a value of the digital signal in a first storage circuit in response to a second timing signal; storing a value of the digital signal in a second storage circuit in response to the second timing signal; generating a detection signal based on the value of the digital signal stored in the second storage circuit; calculating an offset signal indicating a timing difference between the first timing signal and the second timing signal based on the detection signal and based on the value of the digital signal stored in the first storage circuit; and generating adjusted time information based on the time information stored in the first storage circuit and based on the offset signal, wherein the first timing signal and the second timing signal have different frequencies.

19. The method of claim 18 , wherein generating a digital signal in response to a first timing signal comprises generating first count signals having a binary value in response to the first timing signal, and converting the binary value of the first count signals to second count signals having a Gray coded value in response to the first timing signal, wherein the second storage circuit stores the Gray coded value of the second count signals in response to the second timing signal.

20. The method of claim 18 , wherein generating a detection signal based on the value of the digital signal stored in the second storage circuit comprises storing values in a shift register based on the value of the digital signal stored in the second storage circuit, and generating the detection signal based on at least one of the values stored in the shift register.

21. The method of claim 18 , wherein generating a detection signal based on the value of the digital signal stored in the second storage circuit comprises generating count signals using a counter, and resetting the count signals in response to an output signal of the second storage circuit.

22. The method of claim 18 , wherein generating a digital signal in response to a first timing signal comprises toggling the digital signal between two logic states in response to the first timing signal.