Legal claims defining the scope of protection, as filed with the USPTO.
1. A method, comprising: generating a clock signal in a master device having a first power consumption rate; transmitting the clock signal from the master device to a slave device having a second power consumption rate, wherein the first power consumption rate is lower than the second power consumption rate; sampling data received by the slave device, the data being provided by the master device and an antenna associated with the master device; generating first phase error information of the clock signal in the master device; generating second phase error information in the slave device; transmitting the second phase error information from the slave device to the master device; and adjusting the clock signal in response to the generated first and second phase error information, wherein the first phase error information of the clock signal in the master device is based on phase error information generated locally in the master device, and the second phase error information is based on phase error information generated locally in the slave device.
2. The method of claim 1 , further comprising increasing the frequency of the clock signal in the slave device.
3. The method of claim 1 , wherein generating the second phase error information comprises XOR based early/late phase detection.
4. The method of claim 1 , wherein transmitting the second phase error information from the slave device to the master device comprises: multiplexing the second phase error information with data information to produce a composite data stream; and transmitting the composite data stream from the slave device to the master device.
5. A system comprising: one or more antennas to transmit and receive wireless signals via one or more wireless networks; a master device configured to generate a clock signal; a plurality of phase generators incorporated in the master device, at least one of the phase generators to provide control of control data received by the master device and at least another one of the phase generators to provide control of control data transmitted by the master device; and a slave device coupled to the master device and configured to receive the clock signal, the clock signal to control data behavior corresponding to the wireless signals and associated with the master device and the slave device.
6. The system according to claim 5 , wherein the master device comprises a deep submicron technology based device.
7. The system according to claim 5 , wherein the master device is a more power efficient than the slave device.
8. The system according to claim 5 , wherein the master device further comprises at least one phase generator to phase-shift the clock signal to produce a pre-skew clock signal.
9. The system according to claim 5 , wherein the at least one of the phase generators to provide control of control data received by the master device provides the control based on phase error information generated locally in the slave device, and the at least another one of the phase generators to provide control of control data transmitted by the master device provides control the control based on phase error information generated locally in the master device.
10. A system comprising: one or more antennas to transmit and receive wireless signals via one or more wireless networks; a slave device; a master device to couple to the slave device, the master device being more power efficient than the slave device; a plurality of phase generators incorporated in the master device, at least one of the phase generators to provide control of control data received by the master device and at least another one of the phase generators to provide control of control data transmitted by the master device; and a clock generating unit incorporated in the master device to generate a clock signal, the clock signal to control data behavior corresponding to the wireless signals and associated with the master device and the slave device.
11. The system according to claim 10 , wherein the master device comprises a deep submicron technology based device.
12. The system according to claim 10 , wherein the master device comprises a system-on-chip device or a microcontroller.
13. The system according to claim 10 , wherein the slave device comprises an analog front-end device.
14. The system according to claim 11 wherein the slave device includes an analog-to-digital converter.
15. The system according to claim 10 , wherein the slave device further comprises at least one latch that is directly enabled by the clock signal to sample or transmit data to the master device.
16. The system according to claim 10 , wherein the master device further comprises at least one phase generator to phase-shift the clock signal to produce a pre-skew clock signal.
17. The system according to claim 16 , wherein the master device further comprises at least one latch that is directly enabled by the pre-skew clock signal to sample or transmit data to the slave device.
18. The system according to claim 16 , wherein the slave device further comprises a clock and data recovery unit to generate phase error information to be used by the phase generator.
19. The system according to claim 18 , wherein the slave device further comprises at least one multiplexer to multiplex the phase error information with data into a composite data stream that is transmitted to the master device.
20. The system according to claim 16 , wherein the master device further comprises a clock and data recovery unit coupled to the phase generator, wherein the clock and data recovery unit produces at least one control signal to control the phase generator.
21. The system according to claim 10 , wherein the at least one of the phase generators to provide control of control data received by the master device provides the control based on phase error information generated locally in the slave device, and the at least another one of the phase generators to provide control of control data transmitted by the master device provides control the control based on phase error information generated locally in the master device.
Unknown
April 7, 2015
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