9009449

Reducing Power Consumption and Resource Utilization During Miss Lookahead

PublishedApril 14, 2015
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
19 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method for executing program instructions on a processor, comprising: issuing instructions for execution during a normal-execution mode; upon encountering a triggering instruction which causes an unresolved data dependency, speculatively executing subsequent instructions in a lookahead mode to prefetch future load; and when the processor determines that the lookahead mode is unlikely to uncover an additional outer-level cache miss, terminating the lookahead mode and recommencing execution at the triggering instruction in the normal-execution mode after the unresolved data dependency is resolved, wherein the processor determines that the lookahead mode is unlikely to uncover an additional outer-level cache miss based on at least one of: determining that the lookahead mode uncovers the same number of cache misses as were uncovered during a previous lookahead mode which originated from the same triggering instruction; determining that the lookahead mode executes the same number of instructions as were executed until a last outer-level cache miss was uncovered during the previous lookahead mode; and determining that the lookahead mode encounters N branches, wherein the N branches were unresolvable because of data dependency problems and were predicted by a branch predictor with low confidence.

2

2. The method of claim 1 , wherein the processor uses a program counter for the triggering instruction to perform a table lookup to determine the number of cache misses which were uncovered during the previous lookahead mode which originated from the same triggering instruction.

3

3. The method of claim 1 , wherein if no outer-level cache misses were uncovered during the previous lookahead mode which originated from the same triggering instruction, the lookahead mode is not entered.

4

4. The method of claim 1 , wherein the processor uses a program counter for the triggering instruction to perform a table lookup to determine the number of instructions which were executed until a last outer-level cache miss was uncovered during a previous lookahead mode which originated from the same triggering instruction.

5

5. The method of claim 1 , wherein if no outer-level cache misses were uncovered during the previous lookahead mode which originated from the same triggering instruction, the lookahead mode is not entered.

6

6. The method of claim 1 , wherein prior to speculatively executing the instructions in the lookahead mode, the method further comprises generating a checkpoint that can subsequently be used to return execution of the program to the point of the triggering instruction.

7

7. The method of claim 1 , wherein when the unresolved data dependency that originally caused the system to move out of normal-execution mode is finally resolved, the method further comprises resuming execution in the normal-execution mode from the triggering instruction.

8

8. The method of claim 1 , wherein the unresolved data dependency can include: a use of an operand that has not returned from a preceding load miss; a use of an operand that has not returned from a preceding translation lookaside buffer (TLB) miss; a use of an operand that has not returned from a preceding full or partial read-after-write (RAW) from store buffer operation; and a use of an operand that depends on another operand that is subject to an unresolved data dependency.

9

9. An apparatus that executes program instructions, comprising: an execution mechanism configured to issue instructions for execution during a normal-execution mode; and a detection mechanism configured to detect an unresolved data dependency; wherein if an unresolved data dependency is detected during execution of a triggering instruction by a strand, the execution mechanism is configured to speculatively execute subsequent instructions in a lookahead mode to prefetch future loads; and wherein if the execution mechanism determines that the lookahead mode is unlikely to uncover an additional outer-level cache miss, the execution mechanism is configured to terminate the lookahead mode and recommence execution at the triggering instruction in the normal-execution mode after the unresolved data dependency is resolved, wherein the execution mechanism determines that the lookahead mode is unlikely to uncover an additional outer-level cache miss based on at least one of: determining that the lookahead mode uncovers the same number of cache misses as were uncovered during a previous lookahead mode which originated from the same triggering instruction; determining that the lookahead mode executes the same number of instructions as were executed until a last outer-level cache miss was uncovered during the previous lookahead mode; and determining that the lookahead mode encounters N branches, wherein the N branches were unresolvable because of data dependency problems and were predicted by a branch predictor with low confidence.

10

10. The apparatus of claim 9 , wherein the execution mechanism is configured to use a program counter for the triggering instruction to perform a table lookup to determine the number of cache misses which were uncovered during the previous lookahead mode which originated from the same triggering instruction.

11

11. The apparatus of claim 9 , wherein if no outer-level cache misses were uncovered during the previous lookahead mode which originated from the same triggering instruction, the strand does not enter the lookahead mode.

12

12. The apparatus of claim 9 , wherein the execution mechanism is configured to use a program counter for the triggering instruction to perform a table lookup to determine the number of instructions which were executed until a last outer-level cache miss was uncovered during a previous lookahead mode which originated from the same triggering instruction.

13

13. The apparatus of claim 9 , wherein if no outer-level cache misses were uncovered during the previous lookahead mode which originated from the same triggering instruction, the strand does not enter the lookahead mode.

14

14. The apparatus of claim 9 , wherein prior to speculatively executing the instructions in the lookahead mode, the execution mechanism is configured to generate a checkpoint that can subsequently be used to return execution of the program to the point of the triggering instruction.

15

15. The apparatus of claim 9 , wherein when the unresolved data dependency that originally caused the system to move out of normal-execution mode is finally resolved, the execution mechanism is configured to resume execution in the normal-execution mode from the triggering instruction.

16

16. A method for executing program instructions on a processor, comprising: issuing instructions for execution during a normal-execution mode; upon encountering a triggering instruction which causes an unresolved data dependency, speculatively executing subsequent instructions in a lookahead mode to prefetch future loads; and wherein the processor treats strands in the lookahead mode with lower priority than strands in the normal-execution mode by at least of: allocating fewer resources to strands in the lookahead mode as compared to strands in the normal-operating mode; and dropping prefetch requests for strands in the lookahead mode before dropping prefetch requests for strands in the normal-operating mode.

17

17. The method of claim 16 , wherein allocating fewer resources to strands in the lookahead mode as compared to strands in the normal-operating mode involves limiting a strand in the lookahead mode to using fewer pick queue entries than a strand in the normal-operating mode.

18

18. An apparatus that executes program instructions, comprising: an execution mechanism configured to issue instructions for execution during a normal-execution mode; and a detection mechanism configured to detect an unresolved data dependency; wherein if an unresolved data dependency is detected during execution of a triggering instruction by a strand, the execution mechanism is configured to speculatively execute subsequent instructions in a lookahead mode to prefetch future loads; and wherein the execution mechanism is configured to treat strands in the lookahead mode with lower priority than strands in the normal-execution mode by at least one of: allocating fewer resources to strands in the lookahead mode as compared to strands in the normal-operating mode; dropping prefetch requests for strands in the lookahead mode before dropping prefetch requests for strands in the normal-operating mode.

19

19. The apparatus of claim 18 , wherein allocating fewer resources to strands in the lookahead mode as compared to strands in the normal-operating mode involves limiting a strand in the lookahead mode to using fewer pick queue entries than a strand in the normal-operating mode.

Patent Metadata

Filing Date

Unknown

Publication Date

April 14, 2015

Inventors

Yuan C. Chou
Eric W. Mahurin

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Cite as: Patentable. “REDUCING POWER CONSUMPTION AND RESOURCE UTILIZATION DURING MISS LOOKAHEAD” (9009449). https://patentable.app/patents/9009449

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