Iq Gain Imbalance Correction for Receivers Employing Sigma-Delta Analog to Digital Conversion

1. A receiver comprising: a demodulator configured to demodulate a composite signal with magnitude and phase information into an in-phase component and a quadrature component; a first sigma-delta modulator configured to convert the in-phase component into a first discrete time signal comprising a first sequence of one-bit values; a second sigma-delta modulator configured to convert the quadrature component into a second discrete time signal comprising a second sequence of one-bit values; a first transition counter configured to count a number of bit transitions in the first sequence of one-bit values; a second transition counter configured to count a number of bit transitions in the second sequence of one-bit values; and a gain monitor configured to: determine a first power level using the number of bit transitions in the first sequence, determine a second power level using the number of bit transitions in the second sequence, and adjust a gain of at least one of the in-phase component and the quadrature component based on a ratio between the first power level and the second power level.

2. The receiver of claim 1 , wherein the gain monitor comprises: a first adder configured to add a first constant value to the number of bit transitions in the first sequence to determine the first power level; and a second adder configured to add a second constant value to the number of bit transitions in the second sequence to determine the second power level.

3. The receiver of claim 2 , wherein the gain monitor further comprises: a divider configured to divide the first power level by the second power level to determine the ratio.

4. The receiver of claim 3 , wherein the gain monitor adjusts the gain of the in-phase component based on the ratio.

5. The receiver of claim 2 , wherein the gain monitor further comprises: a divider configured to divide the second power level by the first power level to determine the ratio.

6. The receiver of claim 3 , wherein the gain monitor adjusts the gain of the quadrature component based on the ratio.

7. The receiver of claim 1 , wherein the first transition counter comprises: a comparator configured to compare a first one-bit value of the first sequence to a second one-bit value of the first sequence to determine if the first one-bit value is equal to the second one-bit value, wherein the first one-bit value and the second one-bit value are immediately adjacent to each other in the first sequence; and an accumulator configured to increment the number of bit transitions in the first sequence of one-bit values if the first one-bit value is not equal to the second one-bit value as determined by the comparator.

8. The receiver of claim 7 , wherein the first transition counter further comprises: a memory element configured to store the first one-bit value of the first sequence.

9. The receiver of claim 1 , wherein the second transition counter comprises: a comparator configured to compare a first one-bit value of the second sequence to a second one-bit value of the second sequence to determine if the first one-bit value is equal to the second one-bit value, wherein the first one-bit value and the second one-bit value are immediately adjacent to each other in the second sequence; and an accumulator configured to increment the number of bit transitions in the second sequence of one-bit values if the first one-bit value is not equal to the second one-bit value as determined by the comparator.

10. The receiver of claim 9 , wherein the second transition counter further comprises: a memory element configured to store the first one-bit value of the second sequence.

11. A method for calibrating a gain of an in-phase component and a gain of a quadrature component in a receiver: demodulating a composite signal with magnitude and phase information into the in-phase component and the quadrature component; using a first sigma-delta modulator to convert the in-phase component into a first discrete time signal comprising a first sequence of one-bit values; using a second sigma-delta modulator to convert the quadrature component into a second discrete time signal comprising a second sequence of one-bit values; counting a number of bit transitions in the first sequence of one-bit values; counting a number of bit transitions in the second sequence of one-bit values; determining a first power level using the number of bit transitions in the first sequence; determining a second power level using the number of bit transitions in the second sequence; and adjusting a gain of at least one of the in-phase component and the quadrature component based on a ratio between the first power level and the second power level.

12. The method of claim 11 , wherein: the determining the first power level further comprises adding a first constant value to the number of bit transitions in the first sequence to determine the first power level, and the determining the second power level further comprises adding a second constant value to the number of bit transitions in the second sequence to determine the second power level.

13. The method of claim 11 , wherein the adjusting the gain of at least one of the in-phase component and the quadrature component further comprises: dividing the first power level by the second power level to determine the ratio.

14. The method of claim 13 , wherein the gain of the in-phase component is adjusted based on the ratio.

15. The method of claim 11 , wherein the adjusting the gain of at least one of the in-phase component and the quadrature component further comprises: dividing the second power level by the first power level to determine the ratio.

16. The method of claim 15 , wherein the gain of the quadrature component is adjusted based on the ratio.

17. The method of claim 11 , wherein the counting the number of bit transitions in the first sequence of one-bit values further comprises: comparing a first one-bit value of the first sequence to a second one-bit value of the first sequence to determine if the first one-bit value is equal to the second one-bit value, wherein the first one-bit value and the second one-bit value are immediately adjacent to each other in the first sequence; and incrementing the number of bit transitions in the first sequence of one-bit values if the first one-bit value is not equal to the second one-bit value.

18. The method of claim 11 , wherein the counting the number of bit transitions in the second sequence of one-bit values further comprises: comparing a first one-bit value of the second sequence to a second one-bit value of the second sequence to determine if the first one-bit value is equal to the second one-bit value, wherein the first one-bit value and the second one-bit value are immediately adjacent to each other in the second sequence; and incrementing the number of bit transitions in the second sequence of one-bit values if the first one-bit value is not equal to the second one-bit value as determined by the comparator.

19. An apparatus for improving a gain imbalance between an in-phase component and a quadrature component, comprising: a first transition counter configured to count a number of bit transitions in a first sequence of one-bit values provided by a first sigma-delta modulator based on the in-phase component; a second transition counter configured to count a number of bit transitions in a second sequence of one-bit values provided by a second sigma-delta modulator based on the quadrature component; and a gain monitor configured to determine a first power level using the number of bit transitions in the first sequence, determine a second power level using the number of bit transitions in the second sequence, and adjust a gain of at least one of the in-phase component and the quadrature component based on a ratio between the first power level and the second power level.

20. The apparatus of claim 19 , wherein the gain monitor comprises: a first adder configured to add a first constant value to the number of bit transitions in the first sequence to determine the first power level; and a second adder configured to add a second constant value to the number of bit transitions in the second sequence to determine the second power level.