Issue Policy Control Within a Multi-Threaded In-Order Superscalar Processor

1. A multi-threaded in-order superscalar processor comprising: instruction issue circuitry, responsive to a selected issue policy, configured to generate a selection of instructions to issue to respective execution units from among instructions of a plurality of program threads in accordance with said selected issue policy, said selected issue policy corresponding to an algorithm for generating said selection of instructions; and issue policy selection circuitry, responsive to dynamic behaviour of said multi-threaded in-order superscalar processor, configured to select said selected issue policy from among a plurality of issue policies.

2. The multi-threaded in-order superscalar processor as claimed in claim 1 , wherein said plurality of program threads include at least a high priority thread and a low priority thread and said plurality of issue policies include: a primary policy in accordance with which instructions from said high priority thread are issued in preference to instructions from said low priority thread with no assured selection of any program instructions from said low priority thread; and a secondary policy having an assured selection of at least some instructions from said low priority thread.

3. The multi-threaded in-order superscalar processor as claimed in claim 1 , wherein said instructions issue circuitry selects which of said plurality of program threads are active and have instructions selected therefrom in accordance with said selected issue policy.

4. The multi-threaded in-order superscalar processor as claimed in claim 2 , wherein, when said primary policy is selected, said instruction issue circuitry switches between a first sub-state in which no attempt is made to issue instructions from said low priority thread and a second sub-state in which an attempt is made to issue at least one instruction from said low priority thread with each set of instructions to be issued.

5. The multi-threaded in-order superscalar processor, as claimed in claim 4 , wherein said instruction issue circuitry operates in said first sub-state when at least a predetermined number of instructions from said high priority thread are available for attempted issue by said instruction issue circuitry and said instruction issue circuitry operates in said second sub-state when less than said predetermined number of instructions from said high priority thread are available for attempted issue by said instruction issue circuitry.

6. The multi-threaded in-order superscalar processor as claimed in claim 2 , wherein when said secondary policy is selected, said instruction issue circuitry attempts to issue at least one instruction from said high priority thread and said low priority thread with each set of instructions to be issued.

7. The multi-threaded in-order superscalar processor as claimed in claim 2 , wherein, when said primary policy is selected, said issue policy selection circuitry accumulates a count indicative of how many consecutive instruction issue slots are not filled with an instruction from said high priority thread and, when said count reaches a first threshold value, said issue policy selection circuitry selects said secondary policy.

8. The multi-threaded in-order superscalar processor as claimed in claim 7 , wherein, said issue policy selection circuitry selects said primary, policy after a predetermined time of operating with said secondary policy.

9. The multi-threaded in-order superscalar processor as claimed in claim 8 , wherein said issue policy selection circuitry comprises an N-bit saturating counter to accumulate said count, said selection of said secondary policy being made when said N-bit saturating counter saturates.

10. The multi-threaded in-order superscalar processor as claimed in claim 9 , wherein, when said primary policy is selected, if said instruction issue circuitry issues instructions of said high priority thread in all available instruction issue slots, then said issue policy selecting circuitry resets said N-bit saturating counter.

11. The multi-threaded in-order superscalar processor as claimed in claim 9 , wherein said N-bit saturating counter is decremented for each processor cycle when said secondary policy is selected, said selection of said primary policy being made when said N-bit saturated counter reaches a second threshold value.

12. The multi-threaded in-order superscalar processor as claimed in claim 9 , wherein said instruction issue circuitry issues up to two instructions in parallel to said execution units and said N-bit saturating counter is a 2-bit saturating counter.

13. The multi-threaded in-order superscalar processor as claimed in claim 1 , wherein said issue policy selecting circuitry comprises observation circuitry for detecting said dynamic behaviour including at least attempted instruction issue outcome behaviour associated with at least one of said plurality of issue policies.

14. The multi-threaded in-order superscalar processor as claimed in claim 1 , wherein said plurality of program threads include at least a high priority thread and a low priority thread and said plurality of issue policies comprise at least three issue policies including: a primary policy in accordance with which instructions from said high priority thread are issued and no attempt is made to issue instructions from said low priority thread; a secondary policy in accordance with which instructions from said high priority thread and instructions from said low priority thread are issued; and a tertiary policy in accordance with which instructions from said low priority thread are issued and no attempt is made to issue instructions from said high priority thread.

15. The multi-threaded in-order superscalar processor as claimed in claim 14 , wherein said issue policy selecting circuitry operates as a state machine and comprises observation circuitry for detecting said dynamic behaviour including which instruction issue slots are at least capable of being used by instructions of said high priority thread, said observation circuitry triggering said issue policy selecting circuitry to switch said selected issue policy in dependence upon said detected dynamic behaviour to increase issue of instructions from said low priority thread in instruction issue slots not capable of being used by instructions of said high priority thread.

16. The multi-threaded in-order superscalar processor as claimed′ in claim 15 , wherein said observation circuitry detects real issue of instructions of said high priority thread to said instruction slots.

17. The multi-threaded in-order superscalar processor as claimed in claim 15 , wherein said observation circuitry detects speculative behaviour identifying issue slots capable of being used by instructions of said high priority thread and which were not so used.

18. The multi-threaded in-order superscalar processor as claimed in claim 15 , wherein issue policy selected circuitry is arranged such that said switching is subjected to control having a hysteresis characteristic whereby conditions favouring a switch in said selected policy are maintained for a predetermined delay period before said switch is made.

19. The multi-threaded in-order superscalar processor as claimed in claim 15 , wherein said issue policy selecting circuitry includes a primary policy speculative behaviour counter coupled to said instruction issue circuitry and responsive to instructions of said high priority thread when said primary policy is not selected, to accumulate a primary policy speculative behaviour count indicative of occurrences of states in which selection of said primary policy would have resulted successful issue of at least a predetermined number of instructions of said high priority thread in accordance with said primary policy, said issue policy selecting circuitry being responsive to said primary policy speculative behaviour count reaching a first threshold value when said primary policy is not selected to trigger selection of said primary policy.

20. The multi-threaded in-order superscalar processor as claimed in claim 15 , wherein said issue policy selecting circuitry includes a secondary policy speculative behaviour counter coupled to said instruction issue circuitry and responsive to instructions of said high priority thread when said tertiary policy is selected, to accumulate a secondary policy speculative behaviour count indicative of occurrences of states in which selection of said secondary policy would have resulted successful issue of at least a predetermined number of instructions of said high priority thread in accordance with said secondary policy, said issue policy selecting circuitry being responsive to said secondary policy speculative behaviour count reaching a second threshold value when said secondary policy is not selected to trigger selection of said secondary policy.

21. The multi-threaded in-order superscalar processor as claimed in claim 15 , wherein said issue policy selecting circuitry includes a zero issue real behaviour counter coupled to said instruction issue circuitry and responsive to issue of instructions of said high priority thread to accumulate a zero issue behaviour count indicative of occurrences of states in which no instructions of said high priority thread are present in a set of instructions to be issued, said issue policy selecting circuitry being responsive to said zero issue real behaviour count reaching a third threshold value when said tertiary policy is not selected to trigger selection of said tertiary policy.

22. The multi-threaded in-order superscalar processor as claimed in claim 15 , wherein said issue policy selecting circuitry includes a partial issue real behaviour counter coupled to said instruction issue circuitry and responsive to issue of instructions of said high priority thread to accumulate a partial issue behaviour count indicative of occurrences of states in which instructions of said high priority thread partially fill a set of instructions to be issued, said issue policy selecting circuitry being responsive to said partial issue real behaviour count reaching a fourth threshold value when said secondary policy is not selected to trigger selection of said secondary policy.

23. The multi-threaded in-order superscalar processor as claimed in claim 15 , wherein said issue policy selecting circuitry includes a zero-issue real-behaviour counter coupled to said instruction issue circuitry and responsive to issue of instructions of said low priority thread to accumulate a zero issue behaviour count indicative of occurrences of states in which no instructions of said low priority thread are present in a set of instructions to be issued, said issue policy selecting circuitry being responsive to said zero issue real behaviour count reaching a fifth threshold value when said primary policy is not selected to trigger selection of said primary policy.

24. A multi-threaded in-order superscalar processor comprising: instruction issue means for generating, in response to a selected issue policy, a selection of instructions to issue to respective execution units from among instructions of a plurality of program threads in accordance with said selected issue policy, said selected issue policy corresponding to an algorithm for generating said selection of instructions; and issue policy selection means for selecting, in response to dynamic behaviour of said multi-threaded in-order superscalar processor, said selected issue policy from among a plurality of issue policies.

25. A method of operating a multi-threaded in-order superscalar processor, said method comprising the steps of: in response to a selected issue policy, generating a selection of instructions to issue to respective execution units from among instructions of a plurality of program threads in accordance with said selected issue policy, said selected issue policy corresponding to an algorithm for generating said selection of instructions; and in response to dynamic behaviour of said multi-threaded in-order superscalar processor, selecting said selected issue policy from among a plurality of issue policies.

26. The method as claimed in claim 25 , wherein said plurality of program threads include at least a high priority thread and a low priority thread and said plurality of issue policies include: a primary policy in accordance with which instructions from said high priority thread are issued in preference to instructions from said low priority thread with no assured selection of any program instructions from said low priority thread; and a secondary policy having an assured selection of at least some instructions from said low priority thread.

27. The method as claimed in claim 25 , comprising selecting which of said plurality of program threads are active and have instructions selected therefrom in accordance with said selected issue policy.

28. The method as claimed in claim 26 , wherein, when said primary policy is selected, switching between a first sub-state in which no attempt is made to issue instructions from said low priority thread and a second sub-state in which an attempt is made to issue at least one instruction from said low priority thread with each set of instructions to be issued.

29. The method as claimed in claim 28 , comprising operating in said first sub-state when at least a predetermined number of instructions from said high priority thread are available for attempted issue and operating in said second sub-state when less than said predetermined number of instructions from said high priority thread are available for attempted issue.

30. The method as claimed in claim 26 , wherein, when said secondary policy is selected, attempting to issue at least one instruction from said high priority thread and said low priority thread with each set of instructions to be issued.

31. The method as claimed in claim 26 , wherein, when said primary policy is selected, accumulating a count indicative of how many consecutive instruction issue slots are not filled with an instruction from said high priority thread and, when said count reaches a first threshold value, selecting said, secondary policy.

32. The method as claimed in claim 31 , comprising selecting said primary policy after a predetermined time of operating with said secondary policy.

33. The method as claimed in claim 32 , comprising using an N-bit saturating counter to accumulate said count, said selection of said secondary policy being made when said N-bit saturating counter saturates.

34. The method as claimed in claim 33 , wherein, when said primary policy is selected, if instructions of said high priority thread are issued in all available instruction issue slots, then resetting said N-bit saturating counter.

35. The method as claimed in claim 33 , wherein said N-bit saturating counter is decremented for each processor cycle when said secondary policy is selected, said selection of said primary policy being made when said N-bit saturated counter reaches a second threshold value.

36. The method as claimed in claim 33 , wherein up to two instructions are issued in parallel to said execution units and said N-bit saturating counter is a 2-bit saturating counter.

37. The method as claimed in claim 25 , comprising using observation circuitry to detect said dynamic behaviour including at least attempted instruction issue outcome behaviour associated with at least one of said plurality of issue policies.

38. The method as claimed in claim 25 , wherein said plurality of program threads include at least a high priority thread and a low priority thread and said plurality of issue policies comprise at least three issue policies including: a primary policy in accordance with which instructions from said high priority thread are issued and no attempt is made to issue instructions from said low priority thread; a secondary policy in accordance with which instructions from said high priority thread and instructions from said low priority thread are issued; and a tertiary policy in accordance with which instructions from said low priority thread are issued and no attempt is made to issue instructions from said high priority thread.

39. The method as claimed in claim 38 , comprising using observation circuitry to detecting said dynamic behaviour including which instruction issue slots are at least capable of being used by instructions of said high priority thread, said observation circuitry triggering switching of said selected issue policy in dependence upon said detected dynamic behaviour to increase issue of instructions from said low priority thread in instruction issue slots not capable of being used by instructions of said high priority thread.

40. The method as claimed in claim 39 , wherein said observation circuitry detects real issue of instructions of said high priority thread to said instruction slots.

41. The method as claimed in claim 39 , wherein said observation circuitry detects speculative behaviour identifying issue slots capable of being used by instructions of said high priority thread and which were not so used.

42. The method as claimed in claim 39 , wherein said switching is subjected to control having a hysteresis characteristic whereby conditions favouring a switch in said selected policy are maintained for a predetermined delay period before said switch is made.

43. The method as claimed in claim 39 , comprising using a primary policy speculative behaviour counter responsive to instructions of said high priority thread when said primary policy is not selected, to accumulate a primary policy speculative behaviour count indicative of occurrences of states in which selection of said primary policy would have resulted successful issue of at least a predetermined number of instructions of said high priority thread in accordance with said primary policy, said selecting being responsive to said primary policy speculative behaviour count reaching a first threshold value when said primary policy is not selected to trigger selection of said primary policy.

44. The method as claimed in claim 39 , comprising using a secondary policy speculative behaviour counter responsive to instructions of said high priority thread when said tertiary policy is selected, to accumulate a secondary policy speculative behaviour count indicative of occurrences of states in which selection of said secondary, policy would have resulted successful issue of at least a predetermined number of instructions of said high priority thread in accordance with said secondary policy, said selecting being responsive to said secondary policy speculative behaviour count reaching a second threshold value when said secondary policy is not selected to trigger selection of said secondary policy.

45. The method as claimed in claim 39 , comprising using a zero issue real behaviour counter responsive to issue of instructions of said high priority thread to accumulate a zero issue behaviour count indicative of occurrences of states in which no instructions of said high priority thread are present in a set of instructions to be issued, said selecting being responsive to said zero issue real behaviour count reaching a third threshold value when said tertiary policy is not selected to trigger selection of said tertiary policy.

46. The method as claimed in claim 39 , comprising using a partial issue real behaviour counter responsive to issue of instructions of said high priority thread to accumulate a partial issue behaviour count indicative of occurrences of states in which instructions of said high priority thread partially fill a set of instructions to be issued, said selecting being responsive to said partial issue real behaviour count reaching a fourth threshold value when said secondary policy is not selected to trigger selection of said secondary policy.

47. The method as claimed in claim 39 , comprising using a zero-issue real-behaviour counter responsive to issue of instructions of said low priority thread to accumulate a zero issue behaviour count indicative of occurrences of states in which no instructions of said low priority thread are present in a set of instructions to be issued, said selecting being responsive to said zero issue real behaviour count reaching a fifth threshold value when said primary policy is not selected to trigger selection of said primary policy.