Apparatus and Method for Partial Memory Mirroring

1. A processor comprising: a processor core for generating a read or write transaction having a system memory address; a home agent identified to service the read or write transaction based on the system memory address; one or more target address decoders (TADs) associated with the home agent to determine whether the system memory address is within a mirrored memory region or a non-mirrored memory region, wherein: if the system memory address is within a mirrored memory region, then the one or more TADs identifying multiple mirrored memory channels for the read or write transaction; and if the system memory address is not within a mirrored memory region, then the one or more TADs identifying a single memory channel for the read or write transaction.

2. The processor as in claim 1 wherein the transaction comprises a write transaction to write data to the system memory address, wherein the data is written two or more mirrored memory locations over the multiple memory channels identified by the TADs.

3. The processor as in claim 1 wherein the transaction comprises a read transaction to read data from the system memory address, wherein if the system memory address is within a mirrored memory region then the read transaction is first attempted over a first one of the multiple memory channels identified by the TADs.

4. The processor as in claim 3 wherein the read transaction is re-attempted over a second one of the multiple memory channels if the first attempt over the first memory channel results in an error.

5. The processor as in claim 4 wherein the data read from the second memory channel is stored in a memory accessible by the first memory channel in response to the error resulting from the first read attempt over the first memory channel.

6. The processor as in claim 1 wherein each TAD comprises a set of TAD rules, at least TAD rule specifying whether a memory region associated with the TAD is a mirrored memory region or a non-mirrored memory region.

7. The processor as in claim 1 wherein the transaction comprises a read transaction and wherein if the system memory address is not within a mirrored memory region and an error is detected, then poisoned data is returned to a requesting thread.

8. The processor as in claim 1 wherein each memory channel comprises one or more memory sockets into which dual inline memory modules (DIMMs) are plugged.

9. The processor as in claim 1 further comprising: a caching agent to read the system memory address and responsively identify the home agent responsible for servicing the read or write transaction.

10. The processor as in claim 9 wherein the caching agent comprises a system address decoder to identify the home agent.

11. A method comprising: generating a read or write transaction having a system memory address; identifying a home agent to service the read or write transaction based on the system memory address; identifying one or more target address decoders (TADs) associated with the home agent to determine whether the system memory address is within a mirrored memory region or a non-mirrored memory region, wherein: if the system memory address is within a mirrored memory region, then the one or more TADs identifying multiple mirrored memory channels for the read or write transaction; and if the system memory address is not within a mirrored memory region, then the one or more TADs identifying a single memory channel for the read or write transaction.

12. The method as in claim 11 wherein the transaction comprises a write transaction to write data to the system memory address, wherein the data is written two or more mirrored memory locations over the multiple memory channels identified by the TADs.

13. The method as in claim 11 wherein the transaction comprises a read transaction to read data from the system memory address, wherein if the system memory address is within a mirrored memory region then the read transaction is first attempted over a first one of the multiple memory channels identified by the TADs.

14. The method as in claim 13 wherein the read transaction is re-attempted over a second one of the multiple memory channels if the first attempt over the first memory channel results in an error.

15. The method as in claim 14 wherein the data read from the second memory channel is stored in a memory accessible by the first memory channel in response to the error resulting from the first read attempt over the first memory channel.

16. The method as in claim 11 wherein each TAD comprises a set of TAD rules, at least TAD rule specifying whether a memory region associated with the TAD is a mirrored memory region or a non-mirrored memory region.

17. The method as in claim 11 wherein the transaction comprises a read transaction and wherein if the system memory address is not within a mirrored memory region and an error is detected, then poisoned data is returned to a requesting thread.

18. The method as in claim 11 wherein each memory channel comprises one or more memory sockets into which dual inline memory modules (DIMMs) are plugged.

19. The method as in claim 11 further comprising: reading the system memory address and responsively identifying the home agent responsible for servicing the read or write transaction.

20. The method as in claim 19 wherein the operation of reading the system memory address is performed by a caching agent which comprises a system address decoder to identify the home agent.