Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus comprising: multiple oscillators, each oscillator comprising an inverter chain; and combinatorial logic configured to generate a random number comprising one or more bits, the combinatorial logic configured to generate each bit by combining two or more signals from at least two oscillators that have inverter chains with different prime numbers of inverters; wherein, for each bit of the random number, the combinatorial logic is configured to generate multiple initial values, each initial value generated using signals from a different subset of oscillators.
2. The apparatus of claim 1 , wherein the combinatorial logic is configured to generate each bit using signals from a unique combination of oscillators.
3. The apparatus of claim 1 , wherein each subset of oscillators consists of oscillators with inverter chains having different numbers of inverters.
4. The apparatus of claim 1 , wherein, for each bit of the random number, the combinatorial logic is further configured to: sample the initial values to generate sampled values; toggle multiple data bits using the sampled values; and combine the multiple data bits.
5. The apparatus of claim 4 , wherein, for each bit of the random number, the combinatorial logic is further configured to perform a selective inversion by performing one of: a logical XOR operation using the combined data bits and a selective inversion input; and a logical XOR operation using the multiple data bits and the selective inversion input.
6. The apparatus of claim 1 , wherein the oscillators and the combinatorial logic reside in a single integrated circuit device.
7. An apparatus comprising: multiple oscillators, each oscillator comprising an inverter chain; and combinatorial logic configured to generate a random number comprising one or more bits, the combinatorial logic configured to generate each bit by combining two or more signals from at least two oscillators that have inverter chains with different prime numbers of inverters; wherein: the combinatorial logic is configured to combine the two or more signals asynchronously and sample the combined signal synchronously using a synchronous sampling clock; and at least one of the two or more signals is not harmonically related to the synchronous sampling clock.
8. The apparatus of claim 7 , wherein, for each bit of the random number, the combinatorial logic is configured to generate multiple initial values, each initial value generated using signals from a different subset of oscillators.
9. An apparatus comprising: multiple oscillators, each oscillator comprising an inverter chain; and combinatorial logic configured to generate a random number comprising one or more bits, the combinatorial logic configured to generate each bit by combining two or more signals from at least two oscillators that have inverter chains with different prime numbers of inverters; wherein the combinatorial logic comprises one or more bit lanes, each bit lane comprising: an XOR gate configured to combine the two or more signals and generate an initial value; a digital latch configured to sample the initial value; and a toggle-type flip-flop configured to receive an output of the digital latch.
10. The apparatus of claim 9 , wherein: each bit lane comprises multiple XOR gates, multiple digital latches, and multiple toggle-type flip-flops; and each bit lane further comprises (i) an additional XOR gate configured to receive outputs of the toggle-type flip-flops and (ii) an additional digital latch configured to receive an output of the additional XOR gate.
11. An apparatus comprising: multiple oscillators, each oscillator comprising an inverter chain; and combinatorial logic configured to generate a random number comprising one or more bits, the combinatorial logic configured to generate each bit by combining two or more signals from at least two oscillators that have inverter chains with different prime numbers of inverters; wherein: each of at least one of the oscillators comprises multiple taps configured to provide multiple signals from that oscillator; and the multiple signals from one of the oscillators have different asynchronous phases relative to a synchronous sampling clock used by the combinatorial logic.
12. The apparatus of claim 11 , wherein: the random number comprises multiple bits; and the combinatorial logic is configured to use the signal from each tap of each oscillator at most only once in generating the multiple bits.
13. A system comprising: a random number generator comprising: multiple oscillators, each oscillator comprising an inverter chain; and combinatorial logic configured to generate a random number comprising one or more bits, the combinatorial logic configured to generate each bit by combining two or more signals from at least two oscillators that have inverter chains with different prime numbers of inverters; and a processing device configured to receive the random number; wherein: each of at least one of the oscillators comprises multiple taps configured to provide multiple signals from that oscillator; and the multiple signals from one of the oscillators have different asynchronous phases relative to a synchronous sampling clock used by the combinatorial logic.
14. The system of claim 13 , wherein the combinatorial logic is configured to generate each bit using signals from a unique combination of oscillators.
15. A system comprising: a random number generator comprising: multiple oscillators, each oscillator comprising an inverter chain; and combinatorial logic configured to generate a random number comprising one or more bits, the combinatorial logic configured to generate each bit by combining two or more signals from at least two oscillators that have inverter chains with different prime numbers of inverters; and a processing device configured to receive the random number; wherein, for each bit of the random number, the combinatorial logic is configured to generate multiple initial values, each initial value generated using signals from a different subset of oscillators.
16. The system of claim 15 , wherein each subset of oscillators consists of oscillators with inverter chains having different numbers of inverters.
17. The system of claim 15 , wherein, for each bit of the random number, the combinatorial logic is further configured to: sample the initial values to generate sampled values; toggle multiple data bits using the sampled values; and combine the multiple data bits.
18. The system of claim 15 , wherein: each of at least one of the oscillators comprises multiple taps configured to provide multiple signals from that oscillator; and the multiple signals from one of the oscillators have different asynchronous phases relative to a synchronous sampling clock used by the combinatorial logic.
19. A method comprising: receiving multiple signals from multiple oscillators, each oscillator comprising an inverter chain; and generating a random number comprising one or more bits, wherein each bit of the random number is generated by combining two or more signals from at least two oscillators that have inverter chains with different prime numbers of inverters; wherein, for each bit of the random number, generating the random number comprises generating multiple initial values, each initial value generated using signals from a different subset of oscillators.
20. The method of claim 19 , wherein, for each bit of the random number, generating the random number further comprises: sampling the initial values to generate sampled values; toggling multiple data bits using the sampled values; and combining the multiple data bits.
21. The method of claim 19 , wherein each subset of oscillators consists of oscillators with inverter chains having different numbers of inverters.
22. A method comprising: receiving multiple signals from multiple oscillators, each oscillator comprising an inverter chain; and generating a random number comprising one or more bits, wherein each bit of the random number is generated by combining two or more signals from at least two oscillators that have inverter chains with different prime numbers of inverters; wherein: receiving the multiple signals comprises receiving signals from multiple taps in each of at least one of the oscillators; and the signals from the multiple taps in one of the oscillators have different asynchronous phases relative to a synchronous sampling clock used to generate the random number.
23. The method of claim 22 , wherein, for each bit of the random number, generating the random number comprises generating multiple initial values, each initial value generated using signals from a different subset of oscillators.
Unknown
June 16, 2015
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.