Write Operations with Full Sequence Programming for Defect Management in Nonvolatile Memory

1. A method of operating a nonvolatile memory array comprising: receiving a first portion of data to be stored in the nonvolatile memory array; buffering the first portion of data in on-chip data latches; writing the first portion of data from the on-chip data latches to the nonvolatile memory array in Single Level Cell (SLC) format; subsequently receiving a second portion of data to be stored in the nonvolatile memory array; buffering the second portion of data in the on-chip data latches with the first portion of data; subsequently, writing the first and second portions of data together in Multi Level Cell (MLC) format in a word line of an MLC block as lower page and upper page data respectively; subsequently, receiving the second portion of data at least partially in parallel with the storing the first and second portions together in MLC format; subsequently storing the second portion of data in SLC format; subsequently comparing the second portion in MLC format with the second portion in SLC format to determine if the second portion in MLC format meets a standard; and discarding the first and second portions in SLC format only if the second portion in MLC format meets the standard.

2. The method of claim 1 further comprising: suspending the storing of the first and second portions of data together in MLC format in the word line of the MLC block; subsequently, performing a post write read of a third portion of data from another MLC block that was previously filled; subsequently, resuming the storing of the first and second portions together in MLC format in the word line of the MLC block; and in parallel with the resumed storing of the first and second portions together in MLC format in the word line of the MLC block, transferring the third portion of data from the post write read.

3. The method of claim 1 further comprising: comparing the first portion in MLC format with the first portion in SLC format to determine if the first portion in MLC format meets a standard; and discarding the first and second portions in SLC format only if the first portion in MLC format meets the standard.

4. The method of claim 1 wherein the comparing occurs only after the MLC block is full.

5. The method of claim 1 wherein the comparing includes determining a number of bits that are different between the second portion of data in MLC format and the second portion of data in SLC format.

6. The method of claim 5 wherein the standard is a limit for the number of bits that are different.

7. The method of claim 1 further comprising, if the second portion in MLC format does not meet the standard, then discarding the first and second portions in MLC format and using the first and second portions in SLC format.

8. A method of operating a three dimensional nonvolatile memory array comprising: receiving first and second portions of data to be stored in the three dimensional nonvolatile memory array; buffering the first and second portions of data in on-chip data latches; writing the first and second portions of data in a Single Level Cell (SLC) portion of the three dimensional nonvolatile memory array; subsequently writing the first portion of data as lower page data and writing the second portion of data as upper page data together in a row of a Multi Level Cell (MLC) portion of the memory array; maintaining the first portion of data in on-chip data latches throughout a time that extends from the buffering of the first portion of data to the writing the first portion of data as lower page data in the MLC portion of the memory array; and subsequently erasing the first and second portions of data in the SLC portion only after a post write read confirms that the MLC portion of the memory array contains an accurate copy of the first and second portions of data.

9. The method of claim 8 further comprising maintaining the second portion of data in on-chip data latches throughout a time that extends from the buffering of the second portion of data to the writing of the second portion of data as upper page data in the MLC portion of the memory array.

10. The method of claim 8 wherein a die busy signal is maintained until the first portion of data is written as lower page data in the row of the MLC portion of the memory array.

11. The method of claim 10 wherein a die ready signal is initiated when the first portion of data is written as lower page data in the row of the MLC portion of the memory array prior to writing the second portion of data as upper page data in the row of the MLC portion.

12. The method of claim 8 further comprising: suspending the storing of the first and second portions together in the row of the MLC portion; subsequently, performing a post write read of a third portion of data from another MLC block that was previously filled; subsequently, resuming the storing of the first and second portions together in MLC format in the row of the MLC portion; and in parallel with the resumed storing of the first and second portions together in MLC format in the row of the MLC portion, transferring the third portion of data from the post write read.

13. The method of claim 8 wherein the post write read comprises: comparing at least the second portion in MLC format with the second portion in SLC format to determine if the second portion in MLC format meets a standard; and discarding the first and second portions in SLC format only if the second portion in MLC format meets the standard.

14. The method of claim 8 further wherein the post write read samples a block of the MLC portion by reading at least one word line from each group of connected word lines and reading at least one word line from each set of strings of the block.

15. The method of claim 8 further comprising performing a latch transfer operation to move the first portion of data and/or the second portion of data between rows of the on-chip data latches.

16. A three dimensional nonvolatile memory system comprising: a Single Level Cell (SLC) portion of the three dimensional nonvolatile memory array; a Multi Level Cell (MLC) portion of the three dimensional nonvolatile memory array; on-chip data latches that are configured to hold data to be stored in the SLC and MLC portions throughout a time from receiving the data until the data is stored in both SLC and MLC portions; a write circuit that is configured to write lower page data and upper page data from the on-chip data latches to the SLC portion, and then write the lower page data and the upper page data together from the on-chip data latches to the MLC portion; a determination circuit configured to determine whether programmed data in a fully programmed block of the MLC portion meets a standard; and a reclaim circuit that is configured to erase blocks of the SLC portion in response to the determination circuit determining that a corresponding fully programmed block of the MLC portion meets the standard.

17. The three dimensional nonvolatile memory system of claim 16 wherein the write circuit is configured to write the lower page data and the upper page data together along a word line of the MLC portion.

18. The three dimensional nonvolatile memory system of claim 16 further comprising sampling circuits that are configured to sample data of a fully written block of the MLC portion and provide sampled data to the determination circuit for comparison with corresponding data from the SLC portion.