Retention Based Defecting in a Hybrid Memory System

1. A method of operating a hybrid memory system that includes a primary memory and a secondary memory, the method comprising: programming a first page in a memory unit with one or more pages of the secondary memory; recording a first time corresponding to the start of the programming of the first page; recording a second time corresponding to the completion of the programming of the one or more pages; determining a time difference between the first time and the second time; determining if the time difference is greater than a threshold; in response to the time difference being greater than the threshold, disabling a retention based defecting process for the memory unit.

2. The method of claim 1 , wherein the memory unit is a garbage collection unit.

3. The method of claim 1 , wherein the retention based defecting process is enabled if an unrecoverable read error occurs and is not enabled if the time difference being greater than the threshold.

4. The method of claim 1 comprising, in response to the time difference being less than the threshold enabling a retention based defecting process.

5. The method of claim 1 , wherein disabling a retention based defect process comprises continuing to use the memory unit for subsequent data storage in the event of an unrecoverable read error.

6. The method of claim 1 , further comprising: determining one or more characteristics of the memory unit; and disabling a retention based defecting process based on the one or more characteristics.

7. The method of claim 6 wherein the one or more characteristics comprise on or more of the number of program/erase cycles experienced by the memory unit and the temperature of the memory unit.

8. The method of claim 1 , further comprising, in response to the time difference being less than the threshold and a detection of an unrecoverable read error, increasing a counter value for the memory unit.

9. The method of claim 8 further comprising: determining if the counter value for the memory unit is above a threshold; and in response to the counter value for the memory unit being above a threshold, defecting the memory unit.

10. A device, comprising: a hybrid controller configured to manage data transfers between a host processor and a secondary memory, the secondary memory configured to serve as a cache for a primary memory, the hybrid controller configured to: program a first page in a memory unit with one or more pages of the secondary memory; record a first time corresponding to the start of the programming of the first page in the GCU; record a second time corresponding to the completion of the programming of the one or more pages; determine a time difference between the first time and the second time; determine if the time difference is greater than a threshold; in response to the time difference being greater than the threshold, disable a retention based defecting process.

11. The device of claim 10 , wherein the memory unit is a garbage collection unit.

12. The device of claim 10 , wherein the hybrid controller is configured to enable the retention based defecting process if an unrecoverable read error occurs and to not enable the retention based defecting process if the time difference being greater than the threshold.

13. The device of claim 10 comprising, in response to the time difference being less than the threshold, the hybrid controller is configured to enable a retention based defecting process.

14. The device of claim 10 , wherein the hybrid controller is configured to continue to use the memory unit for subsequent data storage in the event of an unrecoverable read error when the retention based defect process is disabled.

15. The device of claim 10 , wherein the hybrid controller is further configured to in response to the time difference being less than the threshold and a detection of an unrecoverable read error, increasing a counter value for the memory unit.

16. The device of claim 15 , wherein the hybrid controller is further configured to: determine if the counter value for the memory unit is above a threshold; and in response to the counter value for the memory unit being above a threshold, defect the memory unit.

17. The device of claim 10 , wherein the hybrid controller is further configured to: determine one or more characteristics of the memory unit; and disable a retention based defecting process based on the one or more characteristics.

18. The device of claim 17 wherein the one or more characteristics comprise one or more of the number of program/erase cycles experienced by the memory unit and the temperature of the memory unit.

19. A controller system for a hybrid memory system, the controller comprising: a hybrid controller configured data transfers between the host processor and a flash memory, the flash memory configured to serve as a cache for a magnetic disk, the hybrid controller configure to: program a first page in a memory unit with one or more pages of the secondary memory; record a first time corresponding to the start of the programming of the first page in the GCU; record a second time corresponding to the completion of the programming of the one or more pages; determine a time difference between the first time and the second time; determine if the time difference is greater than a threshold; in response to the time difference being greater than the threshold, disable a retention based defecting process.

20. The controller system of claim 19 , wherein the memory unit is a garbage collection unit.