Methods and Apparatus for RC Extraction

1. A method for extracting a capacitance from a layout of an integrated circuit (IC), comprising: receiving a computer file of a layout by a computer, wherein the layout comprises a first net and a second net; decomposing by a processing unit of the computer, the first net into a first component and a second component; decomposing by the processing unit of the computer, the second net into a third component and a fourth component; testing by a testing unit, a first condition for the first component and the third component to obtain a first condition result, wherein the testing the first condition for the first component and the third component is to search a library to find whether there is a matching entry in the library that matches the first component and the third component, the first condition result is yes when there is the matching entry found, and no for otherwise; obtaining a first capacitance for the first component and the third component by a first method based on the first condition result, wherein the obtaining the first capacitance for the first component and the third component is based on a pre-calculated capacitance for the matching entry in the library when the first condition result is yes; testing by a testing unit, the first condition for the second component and the fourth component to obtain a second condition result, the second condition result being different from the first condition result; testing by a testing unit, a second condition, based on the second condition result, for the second component and the fourth component to obtain a third condition result, wherein the testing the second condition for the second component and the fourth component is to determine an equation solver to be applied to the second component and the fourth component; obtaining a second capacitance for the second component and the fourth component by a second method different from the first method based on the third condition result, wherein the obtaining the second capacitance for the second component and the fourth component is based on applying the equation solver on the fly to the second component and the fourth component; and determining by a computing unit of the computer, a net capacitance of the first net and the second net based on the first capacitance and the second capacitance.

2. The method of claim 1 , wherein the equation solver is a two-dimensional equation solver.

3. The method of claim 1 , wherein the pre-calculated capacitance is a solution to a 3D equation.

4. The method of claim 1 , wherein the equation solver is a three-dimensional equation solver.

5. The method of claim 1 , wherein the net capacitance is a sum of the first capacitance and the second capacitance.

6. A method for extracting a capacitance from a layout of an integrated circuit (IC), comprising: receiving a computer file of a layout by a computer, wherein the layout comprises a first net and a second net; decomposing by a processing unit of the computer, the first net and the second net into component pairs, each component pair comprising a first component of the first net and a second component of the net; testing by a testing unit, a first condition for each component pair to obtain a first condition result by searching a library to find whether there is a matching entry in the library that matches a tested component pair, wherein the first condition result is yes when there is the matching entry found and no when there is no matching entry found; testing by a testing unit, a second condition for each of a subset of the component pairs having the first condition result of no to obtain a second condition result, wherein testing the second condition determines an equation solver to be applied to each of the subset of the component pairs; obtaining a capacitance for each component pair based on the first condition result and the second condition result, wherein the capacitance is obtained from a pre-calculated capacitance for a respective matching entry in the library when the first condition result is yes, and wherein the capacitance is obtained by applying a respective equation solver on the fly when the first condition result is no; and determining by a computing unit of the computer, a net capacitance of the first net and the second net based on the capacitance of each component pair.

7. The method of claim 6 , wherein the equation solver is a two-dimensional equation solver or a three-dimensional equation solver.

8. The method of claim 6 , wherein testing the first condition for each component pair is to search the library by a length, a width, or a height of each component pair.

9. The method of claim 6 , wherein the net capacitance is a lateral capacitance, an overlay capacitance, or a fringe capacitance.

10. The method of claim 6 , wherein the first net is a first metal layer, and the second net is a second metal layer different from the first metal layer.

11. The method of claim 6 , wherein the first net and the second net are at a middle end of the line (MEOL) metal layer.

12. A system for extracting a capacitance from a layout of an integrated circuit (IC), the system comprising: a receiving unit configured to receive a computer file of a layout comprising a first net and a second net; a processing unit configured to decompose the first net into a first component and a second component, and further configured to decompose the second net into a third component and a fourth component; a memory unit configured to store a library providing a plurality of entries, each entry having a component pair comprising a component of the first net and a component of the second net, and a pre-calculated capacitance for the component pair; a testing unit configured to search the library and to test a first condition for the first component and the third component to obtain a first condition result, configured to test the first condition for the second component and the fourth component to obtain a second condition result, configured to test a second condition, based on the first condition result, for the first component and the third component to obtain a third condition result, and further configured to test the second condition, based on the second condition result, for the second component and the fourth component to obtain a fourth condition result, the second condition being different from the first condition; and a computing unit configured to compute a first capacitance for the first component and the third component by a first method based on the first condition result, compute a second capacitance for the second component and the fourth component by a second method based on the second condition result, and compute a net capacitance of the first net and the second net based on the first capacitance and the second capacitance.

13. The system of claim 12 , wherein the testing unit is further configured to search the library to find whether there is a matching entry in the library that matches the first component and the third component, the first condition result being yes when there is a matching entry found, and no for otherwise.

14. The system of claim 13 , wherein the computing unit is further configured to compute the first capacitance for the first component and the third component based on the pre-calculated capacitance for the matching entry in the library when the first condition result is yes, and compute the first capacitance for the first component and the third component by applying an equation solver on the fly when the first condition result is no.

15. The system of claim 12 , wherein the testing unit is further configured to search the library to find whether there is a matching entry in the library that matches the second component and the fourth component, the second condition result being yes when there is a matching entry found, and no for otherwise.

16. The system of claim 15 , wherein the computing unit is further configured to compute the second capacitance for the second component and the fourth component based on the pre-calculated capacitance for the matching entry in the library when the second condition result is yes, and compute the second capacitance for the second component and the fourth component by applying an equation solver on the fly when the second condition result is no.

17. The system of claim 14 , wherein the fourth condition result determines the equation solver to be applied to the second component and the fourth component to compute the second capacitance when the second condition result is no.

18. The system of claim 14 , wherein the third condition result determines the equation solver to be applied to the first component and the third component to compute the first capacitance when the first condition result is no.

19. The system of claim 12 , wherein the first method is different from the second method when the first condition result is different from the second condition result.

20. The system of claim 12 , wherein the first method is different from the second method when the first condition result is same as the second condition result and the third condition result is different from the fourth condition result.