Semiconductor Device

1. A semiconductor device comprising: a central processing unit; a plurality of peripheral circuits including first and second peripheral circuits; and a conversion portion that has a plurality of input channels including one or more first channels and one or more second channels, a channel selection portion for selecting one of the input channels, and analog-to-digital (A/D) converter for converting a signal input from a selected input channel and outputting a selection signal to the channel selection portion and a completion signal, wherein signal processing in the first peripheral circuit uses an A/D conversion result on a signal input from the one or more first channels, wherein signal processing in the second peripheral circuit uses an A/D conversion result on a signal input from the one or more second channels, wherein the conversion portion receives a scan conversion instruction from the central processing unit, sequentially selects a respective one of the input channels in accordance with a selection signal from the channel selection portion based on a specified selection order, and successively performs A/D conversion, and wherein when the conversion portion performs a scan conversion in response to the scan conversion instruction, the first peripheral circuit receives a conversion result of the one or more first channels in response to the selection signal identified completion of A/D conversion and the second peripheral circuit receives a conversion result of the one or more second channels in response to the selection signal identified completion of A/D conversion for all input channels.

2. The semiconductor device according to claim 1 , wherein the conversion portion notifies the first peripheral circuit of completion of A/D conversion on a signal input to the one or more first channels without using the central processing unit.

3. The semiconductor device according to claim 2 , wherein the conversion portion further includes a plurality of data registers associated with the input channels, wherein each of the data registers stores an A/D conversion result of a signal input to a corresponding input channel, and wherein the first peripheral circuit is capable of reading, without using the central processing unit, A/D conversion results stored in data registers corresponding to the one or more first channels.

4. The semiconductor device according to claim 2 , wherein the conversion portion includes: a plurality of data registers that are provided corresponding to the input channels and each store an A/D conversion result of a signal input from the selected input channel; and one or more flag registers corresponding to the one or more first channels, wherein the first peripheral circuit is capable of reading contents of the one or more flag registers without using the central processing unit, and wherein the A/D converter finishes A/D converting signals input to the one or more first channels, sets a corresponding flag register to a value indicating completion of A/D conversion, and thereby notifies the first peripheral circuit of completion of A/D conversion.

5. The semiconductor device according to claim 4 , wherein the first peripheral circuit is capable of reading, without using the central processing unit, A/D conversion results stored in one or more data registers corresponding to the one or more first channels, and wherein the first peripheral circuit reads an A/D conversion result stored in a data register corresponding to each of the one or more first channels and sets a corresponding flag register to a value indicating incompletion of A/D conversion.

6. The semiconductor device according to claim 2 , further comprising: buffer memory, wherein the first peripheral circuit is capable of reading, without using the central processing unit, data stored in the buffer memory and is capable of detecting whether the buffer memory stores data, and wherein the conversion portion writes an A/D conversion result of a signal input to each of the one or more first channels into the buffer memory and thereby notifies the first peripheral circuit of completion of A/D conversion.

7. The semiconductor device according to claim 2 , wherein the conversion portion includes one or more sample hold circuits for incorporating a signal input to each of the one or more first channels, and wherein the conversion portion A/D converts a signal incorporated into a sample hold circuit corresponding to each of the one or more first channels.

8. The semiconductor device according to claim 2 , further comprising: an interrupt control circuit that outputs an interrupt signal to the central processing unit in response to A/D conversion completion notification received from the conversion portion when the conversion portion receives the scan conversion instruction and finishes A/D converting input signals input to all input channels.

9. A motor controlling system comprising: a motor; a temperature sensor; and a semiconductor device, which comprises a plurality of terminals, an analog-to-digital (A/D) conversion unit comprising a selection unit for selecting one terminal of the plurality of terminals to perform an A/D conversion operation, a plurality of function units, and first plural terminals used for coupling with the motor, and a second terminal used for coupling with the temperature sensor, wherein the A/D conversion unit converts a signal input from a selected input channel and outputs a selection signal to the selection unit and a completion signal, wherein a first function unit of the plurality of function units is a central processing unit for controlling the semiconductor device thereof, wherein a second function unit of the plurality of function units is a data processing unit for a conversion result of the motor, wherein a third function unit of the plurality of function units is a data processing unit for a conversion result of the temperature sensor, wherein in response to receiving a first A/D conversion instruction from the central processing unit, the A/D conversion unit performs the A/D conversion operation for a signal received from respective terminals continuously without an intervening instruction for specifying the terminal from the central processing unit, wherein the second function unit starts a data processing in response to completion of the A/D conversion operation for the first plural terminals without an instruction from the central processing unit, and wherein the third function unit starts a data processing in response to a notification from the central processing unit regarding with a completion of the A/D conversion operation in accordance with the first A/D conversion instruction.

10. The motor controlling system according to claim 9 , wherein the second function unit starts the data processing in response that the selection unit selects the second terminal after selecting the first plural terminals in the A/D conversion operation.

11. The motor controlling system according to claim 10 , wherein a number of the first plural terminals is three, and the motor is three-phase synchronous motor.