Partitioning and Parallel Processing of a Virtual Prototype Simulation of a Hardware Design

1. A method comprising: accessing a first virtual prototype comprising one or more virtual models, wherein the first virtual prototype is configured, upon execution, to perform a first simulation of at least a portion of a hardware design; identifying, by a processor of a computing device, a plurality of checkpoints within the first virtual prototype, wherein each checkpoint of the plurality of checkpoints comprises at least one of a storage state and a behavioral state; determining, by the processor, a plurality of breakpoints for dividing execution of a second virtual prototype into a series of autonomous execution segments, wherein the second virtual prototype is configured, upon execution, to perform a second simulation of the portion of the hardware design, the second virtual prototype comprises one or more virtual models, wherein each virtual model of the second virtual prototype represents a separate portion of the hardware design, and each respective virtual model of the second virtual prototype represents a same portion of the hardware design as a corresponding virtual model of the first virtual prototype, and the plurality of breakpoints correspond to the plurality of checkpoints; for each checkpoint of the plurality of checkpoints, mapping, by the processor, the at least one of the storage state and the behavioral state of the respective checkpoint to a respective execution segment comprising a respective breakpoint of the plurality of breakpoints; causing, by the processor, execution of the second simulation, wherein executing the second simulation comprises executing each execution segment of the series of autonomous execution segments, wherein two or more execution segments of the series of autonomous execution segments are executed concurrently, and respective data is collected during execution of each execution segment of the series of autonomous execution segments; and aggregating, by the processor, the respective data as aggregated data.

2. The method of claim 1 , wherein identifying the plurality of checkpoints comprises estimating execution time of each execution segment of the series of execution segments within a threshold variance.

3. The method of claim 1 , wherein the hardware design comprises an integrated embedded system design.

4. The method of claim 3 , wherein the hardware design comprises a system on a chip (SoC) design.

5. The method of claim 1 , wherein the second virtual prototype is a real time simulation.

6. The method of claim 1 , wherein the first virtual prototype is a loosely-timed prototype or an approximately-timed prototype.

7. The method of claim 1 , wherein the second virtual prototype is a cycle accurate prototype.

8. The method of claim 1 , wherein each checkpoint of the plurality of checkpoints is represented in at least one of a simulated timeframe and an event-driven timeframe.

9. The method of claim 1 , further comprising generating report data based in part upon the aggregated data.

10. The method of claim 9 , wherein the report data is further based upon data collected through execution of the first simulation.

11. The method of claim 10 , wherein: identifying the plurality of checkpoints comprises executing the first simulation; and the data collected through execution of the first simulation comprises the at least one of the storage state and the behavioral state.

12. The method of claim 10 , further comprising validating at least one of the first virtual prototype and the second virtual prototype, wherein validating comprises analyzing the aggregated data in light of the data collected through execution of the first simulation.

13. The method of claim 1 , wherein the first virtual prototype comprises two or more software processes, and identifying the plurality of checkpoints comprises identifying the plurality of checkpoints within a subset of the two or more software processes.

14. The method of claim 1 , further comprising, prior to executing each execution segment of the series of autonomous execution segments, importing initialization data into each execution segment of the series of execution segments.

15. The method of claim 1 , wherein identifying the plurality of checkpoints comprises: recognizing one or more exclusion zones within a code base of the first virtual prototype; and marking the one or more exclusion zones as ineligible for checkpoint identification.

16. The method of claim 15 , wherein each exclusion zone of the one or more exclusion zones comprises a software routine that executes at one of a) varying frequency and b) varying length of time depending upon a level of abstraction of simulation prototype.

17. The method of claim 15 , wherein a first exclusion zone of the one or more exclusion zones comprises an interrupt service routine.

18. The method of claim 1 , further comprising, prior to identifying the plurality of checkpoints, executing the first simulation to determine a total length of simulation.

19. The method of claim 18 , wherein identifying the plurality of checkpoints comprises executing the first simulation while tracking at least one of a program counter and a series of program branches.

20. The method of claim 19 , further comprising, while executing the first simulation, creating a program execution flow log of the first simulation.

21. The method of claim 20 , wherein executing the series of autonomous execution segments comprises, for each execution segment of the series of autonomous execution segments: tracking a program execution flow; and comparing the program execution flow to a portion of the program execution flow log of the first simulation, wherein the portion of the program execution flow log maps to the respective execution segment.

22. The method of claim 21 , wherein tracking the program execution flow comprises tracking the program execution flow using the program counter.

23. The method of claim 21 , wherein tracking the program execution flow comprises tracking the program branches.

24. The method of claim 21 , further comprising, while comparing the program execution flow to the portion of the program execution flow log of the first simulation, identifying a deviation between the program execution flow and the portion of the program execution flow log.

25. A system comprising: a processor; and a memory having instructions stored thereon, wherein the instructions, when executed by the processor, cause the processor to: access a first virtual prototype comprising one or more virtual models, wherein the first virtual prototype is configured, upon execution, to perform a first simulation of at least a portion of a hardware design; identify a plurality of checkpoints within the first virtual prototype, wherein each checkpoint of the plurality of checkpoints comprises at least one of a storage state and a behavioral state; determine a plurality of breakpoints for dividing execution of a second virtual prototype into a series of autonomous execution segments, wherein the second virtual prototype is configured, upon execution, to perform a second simulation of the portion of the hardware design, the second virtual prototype comprises one or more virtual models, wherein each virtual model of the second virtual prototype represents a separate portion of the hardware design, and each respective virtual model of the second virtual prototype represents a same portion of the hardware design as a corresponding virtual model of the first virtual prototype, and the plurality of breakpoints correspond to the plurality of checkpoints; for each checkpoint of the plurality of checkpoints, map the at least one of the storage state and the behavioral state of the respective checkpoint to a respective execution segment comprising a respective breakpoint of the plurality of breakpoints; cause execution of the second simulation, wherein executing the second simulation comprises executing each execution segment of the series of autonomous execution segments, wherein two or more execution segments of the series of autonomous execution segments are executed concurrently, and respective data is collected during execution of each execution segment of the series of autonomous execution segments; and aggregate the respective data as aggregated data.

26. The system of claim 25 , wherein the instructions, when executed, further cause the processor to, for each execution segment of the series of autonomous execution segments, determine one or more end conditions.

27. The system of claim 26 , wherein the one or more end conditions comprises one of a timed event and an untimed event within the execution of the second simulation.

28. The system of claim 26 , wherein identifying the plurality of checkpoints comprises building a warm-up period into each execution segment of the series of autonomous execution segments following a first execution segment of the series of autonomous execution segments, wherein building the warm-up period into a given execution segment comprises determining the one or more end conditions to identify a point in execution after a respective breakpoint representing a begin point of a next execution segment.

29. The system of claim 28 , wherein aggregating the respective data comprises discarding a portion of the respective data corresponding to a respective warm-up period.

30. A non-transitory computer readable medium having instructions stored thereon, wherein the instructions, when executed by a processor, cause the processor to: access a first virtual prototype comprising one or more virtual models, wherein the first virtual prototype is configured, upon execution, to perform a first simulation of at least a portion of a hardware design; identify a plurality of checkpoints within the first virtual prototype, wherein each checkpoint of the plurality of checkpoints comprises at least one of a storage state and a behavioral state; determine a plurality of breakpoints for dividing execution of a second virtual prototype into a series of autonomous execution segments, wherein the second virtual prototype is configured, upon execution, to perform a second simulation of the portion of the hardware design, the second virtual prototype comprises one or more virtual models, wherein each virtual model of the second virtual prototype represents a separate portion of the hardware design, and each respective virtual model of the second virtual prototype represents a same portion of the hardware design as a corresponding virtual model of the first virtual prototype, and the plurality of breakpoints correspond to the plurality of checkpoints; for each checkpoint of the plurality of checkpoints, map the at least one of the storage state and the behavioral state of the respective checkpoint to a respective execution segment comprising a respective breakpoint of the plurality of breakpoints; cause execution of the second simulation, wherein executing the second simulation comprises executing each execution segment of the series of autonomous execution segments, wherein two or more execution segments of the series of autonomous execution segments are executed concurrently, and respective data is collected during execution of each execution segment of the series of autonomous execution segments; and aggregate the respective data as aggregated data.