Latency Built-In Self-Test

1. A system for determining latency, the system comprising: a generator circuit for generating a feedback bit; a first measurement circuit for receiving the feedback bit, the first measurement circuit providing a first time measurement based on the generation of the feedback bit and receiving the feedback bit; a second measurement circuit for receiving a first clock, a second clock, and a third clock, the second measurement circuit providing a second time measurement based on the first clock, the second clock, and the third clock; and a latency generation circuit for receiving the first time measurement and the second time measurement, the latency generation circuit generating a third time measurement based on the first time measurement and the second time measurement.

2. The system of claim 1 , wherein the first measurement circuit determines the first time measurement based on a first delay associated with a first clock edge of the second clock and a second clock edge of the second clock, the first clock edge of the second clock corresponding to the generation of the feedback bit.

3. The system of claim 2 , wherein the second clock edge of the second clock occurs before receiving the feedback bit.

4. The system of claim 1 , wherein the second measurement circuit determines the second time measurement based on a second delay associated with a phase shift of the first clock and the second clock.

5. The system of claim 4 , wherein the second time measurement is further based on a number of clock periods of the third clock corresponding to the second delay.

6. The system of claim 1 , wherein the first time measurement represents more time than the second time measurement.

7. The system of claim 1 , further comprising: a first transmitter for receiving the feedback bit from the generator circuit and providing the feedback bit to the first measurement circuit.

8. The system of claim 7 , further comprising: a latency adjustment circuit for receiving the third time measurement and adjusting a latency of the first transmitter based on the third time measurement.

9. The system of claim 1 , wherein the first clock is associated with a transceiver.

10. A system for determining latencies of transmitters, the system comprising: a first transmitter; a second transmitter; a first measurement circuit to determine a latency of the first transmitter; a second measurement circuit to determine a latency of the second transmitter; and a latency adjustment circuit to adjust the latency of the first transmitter based on the determined latency of the first transmitter and the determined latency of the second transmitter, wherein the latency of the first transmitter is determined based on a first time measurement associated with a feedback bit provided to the first transmitter, and a second time measurement associated with a first clock, a second clock, and a third clock.

11. The system of claim 10 , wherein the latency of the first transmitter is adjusted to correspond to the determined latency of the second transmitter.

12. The system of claim 10 , further comprising: a generator circuit to generate the feedback bit and provide the feedback bit to the first transmitter, wherein the first time measurement is based on the first measurement circuit receiving the feedback bit from the first transmitter.

13. The system of claim 12 , wherein the second time measurement is based on a delay associated with a phase shift of the first clock and the second clock.

14. The system of claim 10 , wherein the third clock has a higher frequency than the first clock and the second clock.

15. A method for determining latency, the method comprising: generating a feedback bit; providing the feedback bit to a first transmitter; receiving the feedback bit from the first transmitter; and determining a latency of the first transmitter based on receiving the feedback bit, wherein the latency of the first transmitter is based on a first time measurement based on receiving the feedback bit, and a second time measurement based on a first clock, a second clock, and a third clock.

16. The method of claim 15 , wherein the second time measurement is based on a delay associated with a phase shift of the first clock and the second clock, the delay determined by a number of clock periods of the third clock corresponding to the delay.

17. The method of claim 15 , wherein the first time measurement is based on a delay associated with a first clock edge of the second clock and a second clock edge of the second clock, the first clock edge of the second clock corresponding to the generation of the feedback bit.

18. The method of claim 15 , further comprising: determining a latency of a second transmitter; determining a latency adjustment value for the first transmitter based on the latency of the second transmitter and the latency of the first transmitter; and adjusting the latency of the first transmitter based on the latency adjustment value.