Pulse Width Modulation Load Share Bus

1. A power supply system, comprising: a plurality of power supply modules having respective power outputs coupled in parallel; each of the plurality of power supply modules having a controller for controlling the power output thereof; each one of the controllers is coupled to a load share bus (LSB) and comprises a digital load share timer, wherein each of the controllers monitors logic levels on the LSB, a one of the controllers asserts a load share signal on the LSB, when the asserted load share signal on the LSB is detected, remaining ones of the controllers start their respective digital load share timers and assert their load share signals on the LSB, and when the load share signal on the LSB is de-asserted the respective digital load share timers stop; wherein each one of the controllers determines from their respective digital load share timers a maximum percent power value being supplied by a one of the plurality of power supply modules; then each one of the controllers compares the maximum percent power value to the percent power value being supplied by a respective one of the plurality of power supply modules; when the maximum percent power value is greater than the percent power values supplied by respective ones of the plurality of power supply modules, then these respective ones of the plurality of power supply modules output powers are increased; and when the maximum percent power value is substantially the same as a percent power value supplied by a one of the plurality of power supply modules, then this respective one of the plurality of power supply modules output power is reduced.

2. The power supply system according to claim 1 , wherein the controller is a pulse width modulation (PWM) controller.

3. The power supply system according to claim 2 , wherein the percent power value is a duty cycle value of a respective PWM controller.

4. The power supply system according to claim 2 , wherein each PWM controller comprises: a period register; a period comparator having first inputs coupled to outputs of the period register; a counter having outputs coupled to second inputs of the period comparator; a duty cycle comparator having first inputs coupled to the outputs of the counter; a duty cycle register having outputs coupled to second inputs of the duty cycle comparator; a driver having an input coupled to an output of the duty cycle comparator and an output coupled to the LSB, wherein when a count value in the counter is less than a duty cycle value in the duty cycle register the driver asserts the load share signal of the respective controller onto the LSB, otherwise the output of the driver is off; and a capture register having inputs coupled to the outputs of the counter, wherein when the load share signal on the LSB is de-asserted the capture register stores the count value of the counter.

5. The power supply system according to claim 4 , wherein the maximum percent power value is determined from the count value in the capture register.

6. The power supply system according to claim 4 , further comprising first and second edge detectors coupled to the LSB, wherein the first edge detector determines when the load share signal is asserted on the LSB and the second edge detector determines when the load share signal is de-asserted on the LSB.

7. The power supply system according to claim 6 , wherein the first edge detector is a falling edge detector and the second edge detector is a rising edge detector.

8. The power supply system according to claim 6 , wherein the first edge detector is a rising edge detector and the second edge detector is a falling edge detector.

9. The power supply system according to claim 6 , further comprising a noise filter coupled between the LSB and the first and second edge detectors.

10. The power supply system according to claim 4 , wherein the driver is an open collector transistor.

11. The power supply system according to claim 4 , wherein the driver is an open drain field effect transistor.

12. The power supply system according to claim 4 , wherein the controller is a microcontroller.

13. The power supply system according to claim 2 , wherein each PWM controller comprises: a period register; a period comparator having first inputs coupled to outputs of the period register; a counter having outputs coupled to second inputs of the period comparator; a duty cycle comparator having first inputs coupled to the outputs of the counter; a duty cycle register having outputs coupled to second inputs of the duty cycle comparator; a normalization circuit for converting a duty cycle value in the duty cycle register to the percent power value; a percent power register having inputs coupled to the normalization circuit and storing the percent power value; a percent power down counter coupled to the percent power register, wherein when a load/start signal is asserted to a load input thereof the percent power down counter loads the percent power value from the percent power register and starts counting down therefrom; a driver having an input coupled to an output of the percent power down counter, wherein when a nonzero count value is in the percent power down counter the driver asserts the load share signal of the respective controller on the LSB, otherwise the output of the driver is off; a load share signal time counter, wherein the load share signal time counter starts counting when the load share signal on the LSB is asserted and stops counting when the load share signal on the LSB is de-asserted, wherein a count result thereof is the maximum percent power value; and a load share comparator having first inputs coupled to outputs from the percent power register and second inputs coupled to outputs from the load share signal time counter.

14. The power supply system according to claim 13 , further comprising first and second edge detectors coupled to the LSB, wherein the first edge detector determines when the load share signal is asserted on the LSB and the load share signal time counter starts counting, and the second edge detector determines when the load share signal time counter stops counting.

15. The power supply system according to claim 14 , wherein the first edge detector is a falling edge detector and the second edge detector is a rising edge detector.

16. The power supply system according to claim 14 , wherein the first edge detector is a rising edge detector and the second edge detector is a falling edge detector.

17. The power supply system according to claim 14 , further comprising a noise filter coupled between the LSB and the first and second edge detectors.

18. The power supply system according to claim 13 , wherein the controller is a microcontroller.

19. A method for balancing power outputs for a plurality of power supply modules in a power supply system, said method comprising the steps of: coupling in parallel power outputs from a plurality of power supply modules; providing a load share bus (LSB) coupled to each of the plurality of power supply modules; detecting assertion of a load share signal on the LSB and starting a digital timer; asserting a unit load share signal on the LSB for a unit time after detection of the load share signal thereon; measuring by a digital timer a time that the load share signal is asserted on the LSB; determining whether the unit time is less than the measured time of the load share signal or if the unit time is substantially the same time as the load share signal; wherein if the unit time is less than the measured time of the load share signal then increase output power of respective ones of the plurality of power supply modules, and if the unit time is substantially the same time as the load share signal then decrease the output power of that respective one of the plurality of power supply modules.

20. The method according to claim 19 , wherein the step of detecting the assertion of the load share signal comprises the step of detecting a change in a logic level of the LSB.

21. The method according to claim 19 , wherein the step of measuring the time that the load share signal is asserted on the LSB comprises the steps of detecting a change on the LSB from a first logic level to a second logic level to start the time measurement and then detecting a change back from the second logic level to the first logic level to stop the time measurement of the load share signal.