Gate Driving Circuit and Organic Electroluminescent Display Apparatus Using the Same

1. A gate driving circuit for driving a light-emitting display apparatus, the gate driving circuit comprising: a first shift register for outputting a first shift register output in response to a first frame start pulse; a second shift register for outputting a second shift register output in response to a second frame start pulse; a first inverter for selectively inverting the first shift register output according to a first inversion control signal; and a second inverter for selectively inverting the second shift register output according to a second inversion control signal, wherein the first shift register and the second shift register independently operate, and the first inverter and the second inverter independently operate, and a first group gate driving signal is output through the first shift register and the first inverter, and a second group gate driving signal is output through the second shift register and the second inverter, wherein the first or second inversion control signal is activated or deactivated according to a transistor type of a pixel circuit, wherein the first or second shift register is configured to operate to be synchronized with a level of at least one corresponding first or second shift register clock signal, while the corresponding first or second frame start pulse is activated, according to a pulse width control of the first or second group gate driving signal, and wherein the first or second shift register is configured to operate to latch at a rising or a falling edge of the at least one corresponding first or second shift register clock signal, while the corresponding first or second frame start pulse is activated, according to the pulse width control of the first or second group gate driving signal.

2. The gate driving circuit of claim 1 , further comprising: a level shifter for adjusting voltage levels of an output of the first inverter and an output of the second inverter; and an output buffer for storing an output of the level shifter and outputting the output of the level shifter as the first and second group gate driving signals.

3. The gate driving circuit of claim 1 , wherein the first shift register is configured to operate in response to at least one first shift register clock signal, and the second shift register is configured to operate in response to at least one second shift register clock signal.

4. The gate driving circuit of claim 1 , wherein the first shift register is configured to adjust a pulse width of the first group gate driving signal in response to a first pulse width control signal, and the second shift register is configured to adjust a pulse width of the second group gate driving signal in response to a second pulse width control signal.

5. The gate driving circuit of claim 4 , wherein the first shift register is configured to operate in response to at least one first shift register clock signal, the second shift register is configured to operate in response to at least one second shift register clock signal.

6. The gate driving circuit of claim 5 , wherein, when a pulse width of the first group gate driving signal is adjusted, the first pulse width control signal is activated and the pulse width of the first group gate driving signal is determined by a pulse width of the first frame start pulse, and when a pulse width of the second group gate driving signal is adjusted, the second pulse width control signal is activated and the pulse width of the second group gate driving signal is determined by a pulse width of the second frame start pulse.

7. The gate driving circuit of claim 1 , wherein the gate driving circuit is configured to select a number or combination of output channels to be activated from among output channels of the first and second group gate driving signals, according to an output channel selection signal.

8. The gate driving circuit of claim 1 , wherein an output order of output channels of the first and second group gate driving signals is controlled according to a scanning direction control signal.

9. The gate driving circuit of claim 1 , wherein the first and second group gate driving signals are sequentially output according to a simultaneous light emission control signal, and wherein the first and second group gate driving signals are concurrently output according to the simultaneous light emission control signal.

10. The gate driving circuit of claim 1 , wherein, when the first or second group gate driving signal is a signal supplied to a pixel circuit realized with a P-type transistor, the corresponding first or second inversion control signal is activated, and the corresponding first or second shift register output is inverted and output from the corresponding first or second inverter.

11. The gate driving circuit of claim 1 , wherein, when the first or second group gate driving signal is a signal supplied to a pixel circuit realized with an N-type transistor, the corresponding first or second inversion control signal is deactivated, and the corresponding first or second shift register output is transmitted as an output from the corresponding first or second inverter.

12. The gate driving circuit of claim 1 , wherein the first group gate driving signal is a scanning signal, and the second group gate driving signal is a light emission control signal.

13. The gate driving circuit of claim 1 , wherein the light-emitting display apparatus is an organic electroluminescent display apparatus.

14. An organic electroluminescent display apparatus comprising: a plurality of pixels located at crossing regions of data lines and scanning lines, each of the pixels comprising an organic light-emitting diode (OLED); a gate driver for outputting scanning signals through the scanning lines to each of the plurality of pixels, and for outputting a light emission control signal through light emission control lines; and a data driver for generating a data signal corresponding to an image and outputting the generated data signal to each of the plurality of pixels through the data lines, wherein the gate driver comprises the gate driving circuit according to claim 1 .