Receiver Circuit and Receiving Method

1. A receiver circuit comprising: an analog to digital converter (ADC) configured to convert an input data signal into sample data in accordance with a clock; a boundary phase computation circuit configured to determine a boundary phase of the input data signal based on the sample data; an eye pattern computation circuit configured to: compute an amplitude of an eye pattern of the input data signal, based on the sample data, the boundary phase, and a phase offset from a first memory; determine a maximum amplitude phase of the eye pattern by computing the amplitude of the eye pattern of the input data signal, while obtaining different phase offsets from the first memory; and estimate, as the maximum amplitude phase, a first amplitude phase that exists in a proximity of a phase intermediate between adjacent boundary phases, compute a first amplitude corresponding to the first amplitude phase, a second amplitude corresponding to a second amplitude phase preceding the first amplitude phase, and a third amplitude corresponding to a third amplitude phase succeeding the first amplitude phase, compare the first amplitude with both of the second amplitude and the third amplitude, and determine, as the maximum amplitude phase, the first amplitude phase when the first amplitude is larger than both of the second amplitude and the third amplitude; and a determination circuit configured to determine a value of the input data signal in the maximum amplitude phase based on the sample data and the maximum amplitude phase.

2. The receiver circuit according to claim 1 , wherein the boundary phase computation circuit, the eye pattern computation circuit and the determination circuit are included in a digital processing circuit.

3. The receiver circuit according to claim 1 , wherein the eye pattern computation circuit is configured to determine the maximum amplitude phase by performing quadratic interpolation processing on the sample data.

4. The receiver circuit according to claim 1 , wherein the eye pattern computation circuit is configured to determine the maximum amplitude phase by performing linear interpolation processing including an extrapolation process on the sample data.

5. The receiver circuit according to claim 1 , wherein the ADC is configured to sample the input data signal at a rate of a half of a unit interval.

6. The receiver circuit according to claim 1 , wherein the eye pattern computation circuit is configured to include an adder circuit to add a phase offset to the boundary phase and output the maximum amplitude phase.

7. The receiver circuit according to claim 1 , further comprising: a second memory configured to store the computed amplitude of the eye pattern of the input data signal in association with the phase offset which is used to compute the amplitude.

8. A receiving method comprising: converting an input data signal into sample data in accordance with a clock from a clock generation circuit; determining a boundary phase of the input data signal based on the sample data; computing an amplitude of an eye pattern of the input data signal based on the sample data, the boundary phase, and a phase offset from a first memory; determining a maximum amplitude phase of the eye pattern of the input data signal by computing the amplitude, while obtaining different phase offsets from the first memory; estimating, as the maximum amplitude phase, a first amplitude phase that exists in a proximity of a phase intermediate between adjacent boundary phases, computing a first amplitude corresponding to the first amplitude phase, a second amplitude corresponding to a second amplitude phase preceding the first amplitude phase and a third amplitude corresponding to a third amplitude phase succeeding the first amplitude phase, comparing the first amplitude with both of the second amplitude and the third amplitude, and determining, as the maximum amplitude phase, the first amplitude phase when the first amplitude is larger than both of the second amplitude and the third amplitude; and determining a value of the input data signal in the maximum amplitude phase based on the sample data and the maximum amplitude phase.

9. The receiving method according to claim 8 , wherein a digital processing circuit performs the determining of the boundary phase, the computing of the eye pattern, the determining of the maximum amplitude phase, and the determining of the value of the input data signal.

10. The receiving method according to claim 8 , further comprising, performing quadratic interpolation processing on the sample data to determine the maximum amplitude phase.

11. The receiving method according to claim 8 , further comprising, performing linear interpolation processing including an extrapolation process on the sample data to determine the maximum amplitude phase.

12. The receiving method according to claim 8 , wherein the input data signal is converted into sample data at a rate of a half of a unit interval by an analog to digital converter (ADC).

13. The receiving method according to claim 8 , further comprising, adding a phase offset to the boundary phase to output the maximum amplitude phase.

14. The receiving method according to claim 8 , further comprising: storing, in a second memory, the computed amplitude of the eye pattern of the input data signal in association with the phase offset which is used to compute the amplitude.