Multi-Wire Single-Ended Push-Pull Link with Data Symbol Transition Based Clocking

1. A method for multi-wire signaling, comprising: converting a sequence of data bits into twelve (12) transition numbers; converting the transition numbers into a sequence of symbols, wherein each of the sequence of symbols is selected based on a corresponding one of the transition numbers and a value of a preceding one of the sequence of symbols; and transmitting the sequence of symbols over two wires using a pair of single-ended drivers, wherein a clock signal is effectively embedded in the sequence of symbols.

2. The method of claim 1 , wherein the conversion from the transition numbers into the sequence of symbols guarantees that each two sequentially occurring symbols in the sequence of symbols are different.

3. The method of claim 1 , wherein converting the transition numbers into the sequence of symbols comprises, for each of the transition numbers: determining an immediate predecessor symbol in the sequence of symbols; and selecting as a next symbol in the sequence of symbols, a symbol identified by using the each transition number as an offset from the immediate predecessor symbol.

4. The method of claim 1 , wherein each symbol in the sequence of symbols is selected from a plurality of available symbols, and wherein each of the plurality of available symbols corresponds to a signaling state of the two wires that is different from the signaling states that correspond to the other symbols in the plurality of available symbols.

5. The method of claim 4 , wherein each of the sequence of symbols is associated with three (3) possible symbol transition states for each transition number.

6. The method of claim 4 , wherein the sequence of symbols is associated with three (3) possible signaling states associated with each symbol in the plurality of available symbols, and wherein the sequence of symbols provides 3 12 different states.

7. The method of claim 6 , wherein the 3 12 different states determine a number of bits that can be encoded in the sequence of symbols.

8. An apparatus, comprising: means for converting a sequence of data bits into twelve (12) transition numbers; means for converting the transition numbers into a sequence of symbols, wherein each of the sequence of symbols is selected based on a corresponding one of the transition numbers and a value of a preceding one of the sequence of symbols; and means for transmitting the sequence of symbols over two wires using a pair of single-ended drivers, wherein a clock signal is effectively embedded in the sequence of symbols.

9. The apparatus of claim 8 , wherein the conversion from the transition numbers into the sequence of symbols guarantees that each two sequentially occurring symbols in the sequence of symbols are different.

10. The apparatus of claim 8 , wherein, for each of the transition numbers, the means for converting the transition numbers into the sequence of symbols is configured to determine an immediate predecessor symbol in the sequence of symbols, and select as a next symbol in the sequence of symbols, a symbol identified by using the each transition number as an offset from the immediate predecessor symbol.

11. The apparatus of claim 8 , wherein each symbol in the sequence of symbols is selected from a plurality of available symbols, and wherein each of the plurality of available symbols corresponds to a signaling state of the two wires that is different from the signaling states that correspond to the other symbols in the plurality of available symbols.

12. The apparatus of claim 11 , wherein each of the sequence of symbols is associated with three (3) possible symbol transition states for each transition number.

13. The apparatus of claim 11 , wherein the sequence of symbols is associated with three (3) possible signaling states associated with each symbol in the plurality of available symbols, and wherein the sequence of symbols provides 3 12 different states.

14. The apparatus of claim 13 , wherein the 3 12 different states determine a number of bits that can be encoded in the sequence of symbols.

15. A transmitter, comprising: a plurality of single-ended drivers; and a processing circuit configured to: convert a sequence of data bits into twelve (12) transition numbers; convert the transition numbers into a sequence of symbols, wherein each of the sequence of symbols is selected based on a corresponding one of the transition numbers and a value of a preceding one of the sequence of symbols; and transmit the sequence of symbols over two wires using two of the plurality of single-ended drivers, wherein a clock signal is effectively embedded in the sequence of symbols.

16. The transmitter of claim 15 , wherein conversion from the transition numbers into the sequence of symbols guarantees that each two sequentially occurring symbols in the sequence of symbols are different.

17. The transmitter of claim 15 wherein, for each of the transition numbers the processing circuit is configured to: determine an immediate predecessor symbol in the sequence of symbols; and select as a next symbol in the sequence of symbols, a symbol identified by using the each transition number as an offset from the immediate predecessor symbol.

18. The transmitter of claim 15 , wherein each symbol in the sequence of symbols is selected from a plurality of available symbols, and wherein each of the plurality of available symbols corresponds to a signaling state of the two wires that is different from the signaling states that correspond to the other symbols in the plurality of available symbols.

19. The transmitter of claim 18 , wherein each of the sequence of symbols is associated with three (3) possible symbol transition states for each transition number.

20. The transmitter of claim 18 , wherein the sequence of symbols is associated with three (3) possible signaling states associated with each symbol in the plurality of available symbols, and wherein the sequence of symbols provides 3 12 different states.

21. The transmitter of claim 20 , wherein the 3 12 different states determine a number of bits that can be encoded in the sequence of symbols.

22. A non-transitory processor-readable storage medium having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to: convert a sequence of data bits into twelve (12) transition numbers; convert the transition numbers into a sequence of symbols, wherein each of the sequence of symbols is selected based on a corresponding one of the transition numbers and a value of a preceding one of the sequence of symbols; and transmit the sequence of symbols over two wires using a pair of single-ended drivers, wherein a clock signal is effectively embedded in the sequence of symbols.

23. The storage medium of claim 22 , wherein conversion from the transition numbers into the sequence of symbols guarantees that each two sequentially occurring symbols in the sequence of symbols are different.

24. The storage medium of claim 22 , wherein the instructions cause the at least one processing circuit to convert the transition numbers into the sequence of symbols by, for each of the transition numbers: determining an immediate predecessor symbol in the sequence of symbols; and selecting as a next symbol in the sequence of symbols, a symbol identified by using the each transition number as an offset from the immediate predecessor symbol.

25. The storage medium of claim 22 , wherein each symbol in the sequence of symbols is selected from a plurality of available symbols, and wherein each of the plurality of available symbols corresponds to a signaling state of the two wires that is different from the signaling states that correspond to the other symbols in the plurality of available symbols.

26. The storage medium of claim 25 , wherein each of the sequence of symbols is associated with three (3) possible symbol transition states for each transition number.

27. The storage medium of claim 25 , wherein the sequence of symbols is associated with three (3) possible signaling states associated with each symbol in the plurality of available symbols, and wherein the sequence of symbols provides 3 12 different states.

28. The storage medium of claim 27 , wherein the 3 12 different states determine a number of bits that can be encoded in the sequence of symbols.

29. A method for performing multi-wire signaling decoding, comprising: receiving a sequence of symbols from two wires using a pair of receivers; extracting a clock signal from the sequence of symbols; converting the sequence of symbols to twelve (12) transition numbers using the clock signal; and converting the transition numbers into data bits, wherein the clock signal is extracted from clock information encoded in transitions between pairs of consecutive symbols in the sequence of symbols.

30. The method of claim 29 , wherein each pair of consecutive symbols in the sequence of symbols comprises two different symbols.

31. The method of claim 29 , wherein converting the sequence of symbols to the transition numbers comprises: using the clock to identify a transition in signaling state of the two wires; and calculating a transition number based on a difference in a first symbol associated with a signaling state occurring before the identified transition and a second symbol associated with a signaling state occurring after the identified transition.

32. The method of claim 31 , wherein the second symbol corresponds to one of three (3) possible signaling states.

33. The method of claim 32 , wherein each possible signaling state of the two wires corresponds to a different one of a plurality of available symbols.

34. An apparatus, comprising: means for receiving a sequence of symbols from two wires using a pair of receivers; means for extracting a clock signal from the sequence of symbols; means for converting the sequence of symbols to twelve (12) transition numbers using the clock signal; and means for converting the transition numbers into data bits, wherein the clock signal is extracted from clock information encoded in transitions between pairs of consecutive symbols in the sequence of symbols.

35. The apparatus of claim 34 , wherein each pair of consecutive symbols in the sequence of symbols comprises two different symbols.

36. The apparatus of claim 34 , wherein the means for converting the sequence of symbols to the transition numbers is configure to: use the clock to identify a transition in signaling state of the two wires; and calculate a transition number based on a difference in a first symbol associated with a signaling state occurring before the identified transition and a second symbol associated with a signaling state occurring after the identified transition.

37. The apparatus of claim 36 , wherein the second symbol corresponds to one of three (3) possible signaling states.

38. The apparatus of claim 37 , wherein each possible signaling state of the two wires corresponds to a different one of a plurality of available symbols.

39. A receiving device, comprising: a plurality of receivers; and a processing circuit configured to: receive a sequence of symbols from two wires using two of the plurality of receivers; extract a clock signal from the sequence of symbols; convert the sequence of symbols to twelve (12) transition numbers using the clock signal; and convert the transition numbers into data bits, wherein the clock signal is extracted from clock information encoded in transitions between pairs of consecutive symbols in the sequence of symbols.

40. The receiving device of claim 39 , wherein each pair of consecutive symbols in the sequence of symbols comprises two different symbols.

41. The receiving device of claim 39 , wherein the processing circuit is further configured to: use the clock to identify a transition in signaling state of the two wires; and calculate a transition number based on a difference in a first symbol associated with a signaling state occurring before the identified transition and a second symbol associated with a signaling state occurring after the identified transition.

42. The receiving device of claim 41 , wherein the second symbol corresponds to one of three (3) possible signaling states.

43. The receiving device of claim 42 , wherein each possible signaling state of the two wires corresponds to a different one of a plurality of available symbols.

44. A non-transitory processor-readable storage medium having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to: receive a sequence of symbols from two wires using a pair of receivers; extract a clock signal from the sequence of symbols; convert the sequence of symbols to twelve (12) transition numbers using the clock signal; and convert the transition numbers into data bits, wherein the clock signal is extracted from clock information encoded in transitions between pairs of consecutive symbols in the sequence of symbols.

45. The storage medium of claim 44 , wherein each pair of consecutive symbols in the sequence of symbols comprises two different symbols.

46. The storage medium of claim 44 , wherein the instructions cause the at least one processing circuit to: use the clock to identify a transition in signaling state of the two wires; and calculate a transition number based on a difference in a first symbol associated with a signaling state occurring before the identified transition and a second symbol associated with a signaling state occurring after the identified transition.

47. The storage medium of claim 46 , wherein the second symbol corresponds to one of three (3) possible signaling states.

48. The storage medium of claim 47 , wherein each possible signaling state of the two wires corresponds to a different one of a plurality of available symbols.