9122401

Efficient Enforcement of Command Execution Order in Solid State Drives

PublishedSeptember 1, 2015
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
18 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method, comprising: storing, in a plurality of queues, by a host, a plurality of storage commands for execution on a non-volatile memory of a storage device, wherein the plurality of storage commands include a respective barrier write command stored to each of the plurality of queues, and wherein at least a subset of the plurality of storage commands is to be executed in accordance with an order-of-arrival in which the subset of the plurality of storage commands is stored; reading, by the storage device, respective storage commands of the plurality of storage commands from each of the plurality of queues; assigning, by the storage device, a respective sequence number to each of the respective storage commands, wherein the respective sequence number marks each of the respective storage commands in accordance with a corresponding order-of-arrival; executing, by the storage device, the respective storage commands in accordance with internal scheduling criteria of the storage device, wherein the internal scheduling criteria permit deviations from the order-of-arrival, and wherein execution of the subset of the plurality of storage commands reflects the order-of-arrival from the host; wherein executing the respective storage commands comprises storing, in the non-volatile memory, respective data and the respective sequence number for each of the respective storage commands; ceasing reads of additional storage commands from a respective queue in response to reaching the barrier write command in the respective queue; and resuming reading of the additional storage commands in each queue of the plurality of queues in response to reaching the barrier write command in all of the queues of the plurality of queues.

2

2. The method according to claim 1 , wherein executing the respective storage commands comprises permitting unblocked execution of the storage commands other than the subset concurrently with execution of the subset of the plurality of storage commands.

3

3. The method according to claim 1 , wherein the non-volatile memory comprises multiple memory devices, and wherein executing the respective storage commands in accordance with the internal scheduling criteria comprises scheduling the respective storage commands for execution across the multiple memory devices.

4

4. The method according to claim 1 , wherein reading the respective storage commands comprises receiving, from the host, an indication that distinguishes the subset of the plurality of storage commands from the plurality of storage commands other than the subset.

5

5. The method according to claim 4 , wherein at least one of the plurality of queues is predefined as an arbitrary queue, wherein storage commands read from the arbitrary queue are permitted to be executed out-of-order, and wherein receiving the indication comprises reading the subset of the plurality of storage commands from a given one of the plurality of queues, wherein the given one is predefined as an in-order queue, wherein storage commands read from the in-order queue are to be executed in accordance with the order-of-arrival.

6

6. The method according to claim 1 , wherein executing the respective storage commands in accordance with the internal scheduling criteria comprises acknowledging a given storage command to the host and recording an execution of the given storage command only upon successful completion of all storage commands of the subset of the plurality of storage commands that precede the given storage command in the order-of-arrival.

7

7. The method according to claim 1 , further comprising: upon recovery from a power disruption in the storage device, identifying a gap in the stored sequence numbers; and disqualifying storage commands in the subset of the plurality of storage commands whose sequence numbers follow the gap.

8

8. The method according to claim 1 , wherein ceasing reads of the additional storage commands from the respective queue comprises incrementing a counter in response to reaching the barrier write command in the respective queue, and wherein resuming reading of the additional storage commands in the plurality of queues comprises resuming reading in response to a value of the counter being greater than or equal to a total number of the plurality of queues.

9

9. An apparatus, comprising: an interface configured to receive, from a host, a plurality of storage commands for execution on a non-volatile memory, wherein at least a subset of the plurality of storage commands are to be executed in accordance with an order-of-arrival in which the subset of the plurality of storage commands is received; a plurality of queues configured to store the received plurality of storage commands, wherein the received plurality of storage commands include a respective barrier write command stored to each queue of the plurality of queues; and a processor configured to: read respective storage commands of the plurality of storage commands from each queue of the plurality of queues; assign a respective sequence number to each of the respective storage commands, wherein the respective sequence number marks each of the respective storage commands in accordance with a corresponding order-of-arrival; execute the respective storage commands in accordance with internal scheduling criteria, wherein the internal scheduling criteria permit deviations from the order-of-arrival, and wherein execution of the subset of the plurality of storage commands reflects the order-of-arrival from the host; store, in the non-volatile memory, respective data and the respective sequence number for each of the respective storage commands in response to the execution of each of the respective storage commands; cease reading of additional storage commands from a respective queue in response to reaching the barrier write command in the respective queue; and resume reading of the additional storage commands in each queue of the plurality of queues in response to reaching the barrier write command in all of the queues of the plurality of queues.

10

10. The apparatus according to claim 9 , wherein the processor is further configured to permit unblocked execution of the plurality of storage commands other than the subset concurrently with execution of the subset of the plurality of storage commands.

11

11. The apparatus according to claim 9 , wherein the non-volatile memory comprises multiple memory devices, and wherein to execute the respective storage commands in accordance with the internal scheduling criteria, the processor is further configured to schedule the respective storage commands for execution across the multiple memory devices.

12

12. The apparatus according to claim 9 , wherein the processor is further configured to receive from the host an indication that distinguishes the subset of the plurality of storage commands from the plurality of storage commands other than the subset.

13

13. The apparatus according to claim 12 , wherein at least one of the plurality of queues is predefined as an arbitrary queue, wherein storage commands read from the arbitrary queue are permitted to be executed out-of-order, and wherein to receive the indication, the processor is further configured to read the subset of the plurality of storage commands from a given one of the plurality of queues, wherein the given one is predefined as an in-order queue, wherein storage commands read from the in-order queue are to be executed in accordance with the order-of-arrival.

14

14. The apparatus according to claim 9 , wherein to execute the respective storage commands in accordance with the internal scheduling criteria, the processor is further configured to acknowledge a given storage command to the host and record an execution of the given storage command only upon successful completion of all storage commands of the subset of the plurality of storage commands that precede the given storage command in the order-of-arrival.

15

15. The apparatus according to claim 9 , wherein the processor is further configured to: upon recovery from a power disruption, identify a gap in the stored sequence numbers; and disqualify storage commands in the subset of the plurality of storage commands whose sequence numbers follow the gap.

16

16. The apparatus according to claim 9 , wherein to cease reading of the additional storage commands from the respective queue, the processor is further configured to increment a counter in response to reaching the barrier write command in the respective queue, and wherein to resume reading of the additional storage commands in each queue of the plurality of queues, the processor is further configured to resume reading in response to a value of the counter being greater than or equal to a total number of the plurality of queues.

17

17. An apparatus, comprising: a non-volatile memory; and a memory controller including a plurality of queues configured to store a plurality of storage commands, wherein the memory controller is configured to: receive, from a host, the plurality of storage commands for execution on the non-volatile memory, wherein the plurality of storage commands include a respective barrier write command stored to each queue of the plurality of queues, and wherein at least a subset of the plurality of storage commands is to be executed in accordance with an order-of-arrival in which the subset of the plurality of storage commands is received; fetch respective storage commands of the plurality of storage commands from each queue of the plurality of queues; assign a respective sequence number to each of the fetched storage commands, wherein the respective sequence number marks each of the fetched storage commands in accordance with a corresponding order-of-arrival; execute the fetched storage commands in accordance with internal scheduling criteria, wherein the internal scheduling criteria permit deviations from the order-of-arrival, and wherein execution of the subset of the plurality of storage commands reflects the order-of-arrival from the host; store, in the non-volatile memory, respective data and the respective sequence number for each of the fetched storage commands in response to the execution of each of the fetched storage commands; halt fetching of the respective storage commands from a respective queue in response to reaching the respective barrier write command in the respective queue; and resume fetching of the respective storage commands in the respective queue of the plurality of queues in response to reaching the barrier command in all the queues of the plurality of queues.

18

18. A system, comprising: a host, which is configured to issue a plurality of storage commands; a plurality of queues configured to store the plurality of storage commands issued by the host, wherein the plurality of storage commands include a respective barrier write command stored to each queue of the plurality of queues, and wherein at least a subset of the plurality of storage commands are to be executed in accordance with an order-of-arrival in which the subset of the plurality of storage commands are received; and a storage device including a non-volatile memory, wherein the storage device is configured to: read respective storage commands of the plurality of storage commands from each queue of the plurality of queues; assign a respective sequence number to each of the respective storage commands, wherein the respective sequence number marks each of the respective storage commands in accordance with a corresponding order-of-arrival; execute the respective storage commands in accordance with internal scheduling criteria of the storage device, wherein the internal scheduling criteria permit deviations from the order-of-arrival, and wherein execution of the subset of the plurality of storage commands reflects the order-of-arrival from the host; store, in the non-volatile memory, respective data and the respective sequence number for each of the respective storage commands in response to the execution of each of the respective storage commands; halt reading of additional storage commands from a respective queue in response to reaching the barrier write command in the respective queue; and resume reading of the additional storage commands in each queue of the plurality of queues in response to reaching the barrier write command in all the queues of the plurality of queues.

Patent Metadata

Filing Date

Unknown

Publication Date

September 1, 2015

Inventors

Etai Zaltsman
Oren Golov
Ori Moshe Stern
Shai Ojalvo

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Cite as: Patentable. “EFFICIENT ENFORCEMENT OF COMMAND EXECUTION ORDER IN SOLID STATE DRIVES” (9122401). https://patentable.app/patents/9122401

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