Lsic Designing Apparatus, Lsic Designing Method, and Program

1. An LSIC (Large Scale Integrated Circuit) designing apparatus comprising: circuitry configured to: input input/output flow information describing input/output flows of signals between function blocks included in an LSIC to be designed, wherein the input/output flows of signals are described in a format of a relational expression indicating a connection of the signals between the function blocks; analyze the inputted input/output flow information; correlate two or more function blocks described in the input/output flow information which output signals of a same type, to one function block that inputs the signals; generate a selector module of a selector that matches the input/output flows of signals between the correlated function blocks; generate a control register for the generated selector module; input CPU (Central Processing Unit) bus interface information; generate a CPU bus interface based on the inputted CPU bus interface information; generate a macro module including the selector module and a function block connected to outputs of the selector module, for accessing the control register for the selector module via the CPU bus interface; and generate input/output flow information describing the input/output flow of a signal between the macro module and a function block connecting the signal to the macro module, based on the input/output flow information describing input/output flows of signals between the function blocks.

2. The LSIC designing apparatus of claim 1 , wherein the circuitry is further configured to: input the input/output flow information describing the input/output flows of signals of different types between function blocks; analyze the input/output flow information and correlate two or more function blocks that input/output signals of the same type; and generate the selector module of the selector having an input pin for each of the correlated two or more function blocks that output signals, and an output pin for each of the correlated two or more function blocks that input signals.

3. The LSIC designing apparatus of claim 1 , wherein the circuitry is further configured to input the input/output flow information describing the input/output flows of signals between function blocks which include IPs (Intellectual Properties).

4. The LSIC designing apparatus of claim 1 , wherein the circuitry is further configured to: input the input/output flow information describing the input/output flows of signals of different types between function blocks; analyze the input/output flow information, and generate a plurality of selector modules, each corresponding to a different selector; analyze the input/output flow information, and correlate two or more function blocks that input/output signals of the same type; select the selector module of the selector that matches the input/output flows of signals between the correlated two or more function blocks, from among the plurality of selector modules, for each of the types of signals; and generate the macro module, using the selector module selected for each of the types of signals.

5. An LSIC (Large Scale Integrated Circuit) designing method performed by a computer including circuitry, comprising: inputting, by the circuitry, input/output flow information describing input/output flows of signals between function blocks included in an LSIC to be designed, wherein the input/output flows of signals are described in a format of a relational expression indicating a connection of the signals between the function blocks; analyzing, by the circuitry, the inputted input/output flow information; correlating, by the circuitry, two or more function blocks described in the input/output flow information which output signals of a same type, to one function block that inputs the signals; generating, by the circuitry, a selector module of a selector that matches the input/output flows of signals between the correlated function blocks; generating, by the circuitry, a control register for the generated selector module; inputting, by the circuitry, CPU (Central Processing Unit) bus interface information; generating, by the circuitry, a CPU bus interface based on the inputted CPU bus interface information; generating, by the circuitry, a macro module including the selector module and a function block connected to outputs of the selector module, for accessing the control register for the selector module via the CPU bus interface; and generating, by the circuitry, input/output flow information describing the input/output flow of a signal between the macro module and a function block connecting the signal to the macro module, based on the input/output flow information describing input/output flows of signals between the function blocks.

6. A non-transitory computer readable medium including a program recorded thereon, the program configured to perform a method when executed on a computer, the method comprising: inputting input/output flow information describing input/output flows of signals between function blocks included in an LSIC (Large Scale Integrated Circuit) to be designed, wherein the input/output flows of signals are described in a format of a relational expression indicating a connection of the signals between the function blocks; analyzing the inputted input/output flow information; correlating two or more function blocks described in the input/output flow information which output signals of a same type, to one function block that inputs the signals; generating a selector module of a selector that matches the input/output flows of signals between the correlated function blocks; generating a control register for the generated selector module; inputting CPU (Central Processing Unit) bus interface information; generating a CPU bus interface based on the inputted CPU bus interface information; generating a macro module including the selector module and a function block connected to outputs of the selector module, for accessing the control register for the selector module via the CPU bus interface; and generating input/output flow information describing the input/output flow of a signal between the macro module and a function block connecting the signal to the macro module, based on the input/output flow information describing input/output flows of signals between the function blocks.