Reduced Contention Storage for Channel Coding

1. A decoder for decoding received data encoded with a concatenated code, the code being generated by using a code generation interleaving operation, comprising: a storage input interleaver for storage-interleaving of the received data using a storage interleaving operation, wherein the received data comprises a serial data stream and the storage interleaving operation comprises reordering data elements of the serial data stream to form storage-interleaved data; a data memory coupled to an output of the storage input interleaver for temporary storage of the storage-interleaved data; a first storage output interleaver coupled to an output of the data memory for interleaving of the storage-interleaved data read from the data memory, wherein interleaving comprises reordering of the storage-interleaved data by applying a permutation to reconstruct the received data; one or more processors coupled to an output of the first storage output interleaver to access the data memory via the first storage output interleaver, wherein the one or more processors receive and operate on the reconstructed received data to form a sequence of reliability data, wherein the sequence of reliability data and the received data are different; and a second storage output interleaver coupled to an output of the data memory for interleaving of the storage-interleaved data read from the data memory; wherein the interleaving operation of the second storage output interleaver is a concatenation of the code generation interleaving operation and the inverse of the storage interleaving operation.

2. The decoder of claim 1 , wherein the data memory comprises a plurality of buffers.

3. The decoder of claim 2 , wherein each buffer is configured to be accessed by one processor on a given clock cycle.

4. The decoder of claim 1 , wherein the storage interleaving operation is identical to the code generation interleaving operation.

5. The decoder of claim 1 , wherein the storage interleaving operation is different than the code generation interleaving operation.

6. The decoder of claim 1 , wherein the interleaving operation of the first storage output interleaver is the inverse of the storage interleaving operation of the storage input interleaver.

7. The decoder of claim 1 , wherein the storage interleaving operation is configured such that a number of collisions when reading the storage-interleaved data from the data memory via the first storage output interleaver plus the number of collisions when reading the storage-interleaved data from the data memory via the second storage output interleaver is less than the number of collisions when reading data, which have been written to the data memory without using a storage interleaving operation, from the data memory via a storage output interleaver using the code generation interleaving operation.

8. A method of decoding received data encoded with a concatenated code, the code being generated by using a code generation interleaving operation, comprising: storage-interleaving the received data using a storage interleaving operation, wherein the received data comprises a serial data stream and the storage-interleaving operation comprises reordering data elements of the serial data stream to form storage-interleaved data; writing the storage-interleaved data to a data memory; interleaving the storage-interleaved data read from the data memory using a first storage output interleaving operation which comprises applying a permutation to reconstruct the received data; processing the reconstructed received data by one or more processors to form a sequence of reliability data, wherein the sequence of reliability data and the received data are different; and interleaving the storage-interleaved data read from the data memory using a second storage output interleaving operation to form re-ordered data, wherein the second interleaving operation is a concatenation of the code generation interleaving operation and the inverse of the storage interleaving operation.

9. The method of claim 8 , wherein the data memory comprises a plurality of buffers, the method further comprising: accessing each buffer by one processor at most on a given clock cycle for processing the re-ordered data.

10. The method of claim 8 , wherein the storage interleaving operation is identical to the code generation interleaving operation.

11. The method of claim 8 , wherein the first storage output interleaving operation is the inverse of the storage interleaving operation.

12. The method of claim 8 , wherein the storage interleaving operation is configured such that a number of collisions when reading the storage-interleaved data from the data memory using the first storage output interleaving operation plus the number of collisions when reading the storage-interleaved data from the data memory using the second storage output interleaving operation is less than the number of collisions when reading data, which have been written to the data memory without using a storage interleaving operation, from the data memory using the code generation interleaving operation.

13. The decoder of claim 1 , wherein the data elements of the serial data stream are reordered in time.

14. The decoder of claim 1 , wherein the data elements of the serial data stream are reordered with respect to each other.