Integrated Circuit for Spreading Response Signal

1. An integrated circuit for controlling a process comprising: receiving control information transmitted on one or a plurality of control channel elements (CCEs) with consecutive CCE number(s), CCEs being numbered sequentially from one; first-spreading a response signal with a sequence defined by a cyclic shift value that is determined among a plurality of cyclic shift values from an index of physical uplink control channel (PUCCH), which is associated with a first CCE number of said one or a plurality of CCEs; and second-spreading the first-spread response signal with an orthogonal sequence that is determined among a plurality of orthogonal sequences from the index; wherein, one of cyclic shift values used for an orthogonal sequence is determined from an index of the PUCCH, which is associated with an odd CCE number, and another one of the cyclic shift values used for the same orthogonal sequence is determined from an index of the PUCCH, which is associated with an even CCE number, and the first CCE number is restricted to be an odd number when the control information is transmitted on the plurality of CCEs.

2. The integrated circuit according to claim 1 , wherein one of two cyclic shift values that are used for the same orthogonal sequence and that are next to each other with a set interval is determined from the index of the PUCCH, which is associated with an odd CCE number and the other of the two cyclic shift values is determined from the index of the PUCCH, which is associated with an even CCE number.

3. The integrated circuit according to claim 1 , wherein the first CCE number is not restricted to be either an odd number or an even number when the control information is transmitted on one CCE.

4. The integrated circuit according to claim 1 , wherein the PUCCH is used for transmission of the response signal, and the first CCE number, with which an index of the PUCCH that is used only when the control information is transmitted on one CCE is associated, is restricted to be an even number.

5. The integrated circuit according to claim 1 , wherein the PUCCH is used for transmission of the response signal, and probabilities to be used are different between the PUCCH associated with an odd CCE number and the PUCCH associated with an even CCE number.

6. The integrated circuit according to claim 1 , wherein the index of the PUCCH is consecutively associated with the CCE number, and the cyclic shift values used for the same orthogonal sequence are respectively determined from indices of the PUCCH, which are consecutive in a direction in which the cyclic shift value is shifted.

7. The integrated circuit according to claim 1 , wherein the process further comprises transmitting the response signal using the PUCCH.

8. The integrated circuit according to claim 1 , wherein the process further comprises determining whether or not the received control information is directed to a radio communication apparatus, and determining the index of the PUCCH, which is associated with the first CCE number on which the control information directed to the radio communication apparatus is transmitted.

9. The integrated circuit according to claim 1 , wherein three orthogonal sequences are used.

10. The integrated circuit according to claim 1 , wherein a sequence having a length 12 is used as the sequence defined by the cyclic shift value, and a sequence having a length 4 is used as the orthogonal sequence.

11. The integrated circuit according to claim 1 , wherein the response signal is a response signal of ACK or NACK.

12. The integrated circuit according to claim 1 , wherein one of orthogonal sequences used for a cyclic shift value is determined from an index of the PUCCH, which is associated with an odd CCE number, and another one of the orthogonal sequences used for the same cyclic shift value is determined from an index of the PUCCH, which is associated with an even CCE number.

13. The integrated circuit according to claim 12 , wherein a number of the plurality of cyclic shift values is 12.

14. The integrated circuit according to claim 1 , wherein: one of two cyclic shift values that are used for the same orthogonal sequence and that are next to each other with a set interval is determined from the index of the PUCCH, which is associated with an odd CCE number and the other of the two cyclic shift values is determined from the index of the PUCCH, which is associated with an even CCE number; and one of two orthogonal sequences that are used for a cyclic shift value and whose sequence indices are different by one is determined from the index of the PUCCH, which is associated with an odd CCE number, and the other of the two orthogonal sequences is determined from the index of the PUCCH, which is associated with an even CCE number.

15. An integrated circuit for controlling a process comprising: receiving control information transmitted on one or a plurality of control channel elements (CCEs) with consecutive CCE number(s); first-spreading a response signal with a sequence defined by a cyclic shift value that is determined among a plurality of cyclic shift values from an index of physical uplink control channel (PUCCH), which is associated with a first CCE number of said one or a plurality of CCEs; and second-spreading the first-spread response signal with an orthogonal sequence that is determined among a plurality of orthogonal sequences from the index; wherein the PUCCH is used for transmission of the response signal, and one of cyclic shift values used for an orthogonal sequence is determined from an index of the PUCCH, which is used when the control information is transmitted on the plurality of CCEs, and another one of the cyclic shift values used for the same orthogonal sequence is determined from an index of the PUCCH, which is used when the control information is transmitted on one CCE.

16. The integrated circuit according to claim 15 , wherein one of two cyclic shift values that are used for the same orthogonal sequence and that are next to each other with a set interval is determined from the index of the PUCCH, which is used when the control information is transmitted on the plurality of CCEs, and the other of the two cyclic shift values is determined from the index of the PUCCH, which is used when the control information is transmitted on one CCE.

17. The integrated circuit according to claim 15 , wherein CCEs are numbered sequentially from one, and the first CCE number is restricted to be an odd number when the control information is transmitted on the plurality of CCEs.

18. The integrated circuit according to claim 15 , wherein CCEs are numbered sequentially from one, the first CCE number is restricted to be an odd number when the control information is transmitted on the plurality of CCEs, and the first CCE number is not restricted to be either an odd number or an even number when the control information is transmitted on one CCE.

19. The integrated circuit according to claim 15 , wherein CCEs are numbered sequentially from one, the first CCE number is restricted to be an odd number when the control information is transmitted on the plurality of CCEs, and the first CCE number, with which the PUCCH that is used only when the control information is transmitted on one CCE is associated, is restricted to be an even number.

20. The integrated circuit according to claim 15 , wherein one of orthogonal sequences used for a cyclic shift value is determined from an index of the PUCCH, which is used when the control information is transmitted on the plurality of CCEs, and another one of the orthogonal sequences used for the same cyclic shift value is determined from an index of the PUCCH, which is used when the control information is transmitted on one CCE.

21. The integrated circuit according to claim 15 , wherein: one of two cyclic shift values that are used for the same orthogonal sequence and that are next to each other with a set interval is determined from the index of the PUCCH, which is used when the control information is transmitted on the plurality of CCEs, and the other of the two cyclic shift values is determined from the index of the PUCCH, which is used when the control information is transmitted on one CCE; and one of two orthogonal sequences that are used for a cyclic shift value and whose sequence indices are different by one is determined from the index of the PUCCH, which is used when the control information is transmitted on the plurality of CCEs, and the other of the two orthogonal sequences is determined from the index of the PUCCH, which is used when the control information is transmitted on one CCE.

22. The integrated circuit according to claim 15 , wherein: CCEs are numbered sequentially from one; the first CCE number is restricted to be an odd number when the control information is transmitted on the plurality of CCEs; and one of orthogonal sequences used for a cyclic shift value is determined from an index of the PUCCH, which is used when the control information is transmitted on the plurality of CCEs, and another one of the orthogonal sequences used for the same cyclic shift value is determined from an index of the PUCCH, which is used when the control information is transmitted on one CCE.

23. An integrated circuit for controlling a process comprising: receiving control information transmitted on one or a plurality of control channel elements (CCEs) with consecutive CCE number(s); first-spreading a response signal with a sequence defined by a cyclic shift value that is determined among a plurality of cyclic shift values from an index of physical uplink control channel (PUCCH), which is associated with a first CCE number of said one or a plurality of CCEs; and second-spreading the first-spread response signal with an orthogonal sequence that is determined among a plurality of orthogonal sequences from the index, wherein: one of cyclic shift values used for an orthogonal sequence is determined from an index of the PUCCH, which is associated with an odd CCE number, and another one of the cyclic shift values used for the same orthogonal sequence is determined from an index of the PUCCH, which is associated with an even CCE number; and one of orthogonal sequences used for a cyclic shift value is determined from an index of the PUCCH, which is associated with an odd CCE number, and another one of the orthogonal sequences used for the same cyclic shift value is determined from an index of the PUCCH, which is associated with an even CCE number.

24. The integrated circuit according to claim 23 , wherein: one of two cyclic shift values that are used for the same orthogonal sequence and that are next to each other with a set interval is determined from the index of the PUCCH, which is associated with an odd CCE number and the other of the two cyclic shift values is determined from the index of the PUCCH, which is associated with an even CCE number; and one of two orthogonal sequences that are used for the same cyclic shift value and whose sequence indices are different by one is determined from the index of the PUCCH, which is associated with an odd CCE number, and the other of the two orthogonal sequences is determined from the index of the PUCCH, which is associated with an even CCE number.

25. The integrated circuit according to claim 23 , wherein a number of the plurality of cyclic shift values is 12.