Packet Detector

1. A system configured for OFDM communication comprising: a transceiver including a receiver adapted to receive at least one packet including a header portion and preamble portion, wherein: the preamble portion includes a plurality of OFDM symbols that were modulated using a constellation scrambler, and the header portion of the packet contains one or more bit fields that contain information that can be used to determine a value of a seed that was used to generate the preamble portion of the packet, and the value of the seed is usable to determine whether the packet is an out-of-domain packet or an in-domain packet.

2. The system of claim 1 , wherein the transceiver includes an ASIC.

3. The system of claim 1 , wherein the transceiver includes a digital signal processor.

4. The system of claim 1 , wherein the transceiver further performs one or more cross-correlations to determine whether the packet was from a transceiver or endpoint that is from an out-of-domain network or from an in-domain network.

5. The system of claim 1 , wherein the transceiver further learns an out-of-domain seed after receiving a first out-of-domain packet and decoding the header portion of that packet, and after learning the out-of-domain seed, the receiver sending a packet indicating the value of the out-of-domain seed to a local master.

6. A system configured for OFDM communication comprising: a transceiver that includes a receiver capable of receiving a packet including a header portion and a preamble portion and capable of detecting the packet using the preamble portion, wherein: the preamble portion was generated using an LFSR (Linear Feedback Shift Register) generator that was initialized with a seed, the header portion of the packet contains one or more bit fields that contain information that can be used to determine a value of the seed used to generate the preamble portion of the packet, and the value of the seed is usable to determine whether the packet is an out-of-domain packet or an in-domain packet.

7. The system of claim 6 , wherein the transceiver includes an ASIC.

8. The system of claim 6 , wherein the transceiver includes a digital signal processor.