Clock Control and Power Management for Semiconductor Apparatus and System

1. A semiconductor apparatus comprising; a circuit including a predetermined function; a clock generating circuit that generates a clock signal supplied to the circuit; a clock control circuit that outputs: a plurality of control signals to the clock generating circuit, a first signal that indicates when a frequency of the clock signal is being changed from a predetermined frequency to a higher frequency, and a second signal that indicates when the clock signal is being supplied to the circuit; and a notification signal generating circuit, coupled to the clock control circuit, that generates a notification signal for notifying a power supply apparatus when the clock signal frequency is being changed based on the first signal, and when the clock signal is being supplied to the circuit based on the second signal.

2. The semiconductor apparatus according to claim 1 , wherein a power supply voltage to be supplied to the circuit is adjusted according to the notification signal.

3. The semiconductor apparatus according to claim 1 , further comprising: a power control circuit that controls power supplied to the circuit, wherein the notification signal notifies when the power control circuit is performing power control.

4. The semiconductor apparatus according to claim 3 , wherein the notification signal generating circuit generates the notification signal when the power control circuit controls the circuit so that the power is supplied to the circuit.

5. The semiconductor apparatus according to claim 3 , wherein the notification signal generating circuit generates the notification signal when the power control circuit controls the circuit so that the power is supplied to the circuit.

6. The semiconductor apparatus according to claim 3 , wherein the power control circuit comprises a state machine, and the notification signal generating circuit generates the notification signal according to a state of the state machine.

7. The semiconductor apparatus according to claim 6 , wherein the notification signal generating circuit generates the notification signal in a period when the state machine performs a process to supply the power to the circuit.

8. The semiconductor apparatus according to claim 1 , wherein the notification signal notifies that an operating current of the circuit has increased.

9. The semiconductor apparatus according to claim 1 , wherein the clock control circuit comprises a state machine having a plurality of states including a clock frequency change process state and a clock supply process state, the first signal is output during the clock frequency change process state, and the second signal is output during the clock supply process state.

10. The semiconductor apparatus according to claim 9 , wherein the notification signal generating circuit generates the notification signal in a period when the state machine performs a process to increase a frequency of the clock signal supplied to the circuit to be higher than a predetermined frequency.

11. The semiconductor apparatus according to claim 9 , wherein the notification signal generating circuit generates the notification signal in a period when the state machine performs a process to supply the clock signal to the circuit.

12. The semiconductor apparatus according to claim 9 , wherein the plurality of states includes a clock stop process state and an idle state.

13. The semiconductor apparatus according to claim 1 , wherein the circuit comprises a processor including a CPU and a cache memory and a memory access detecting unit that detects the number of accesses to the cache memory by the CPU and calculates an expected amount of current consumption in the processor according to the number of accesses, and the clock control circuit controls the clock generating circuit so that the frequency of the clock signal supplied to the circuit is reduced when the calculated expected amount of current consumption exceeds a predetermined reference value.

14. The semiconductor apparatus according to claim 1 , further comprising: a first terminal that supplies the power supply voltage to the circuit; and a second terminal that is supplied with the notification signal.

15. The semiconductor apparatus according to claim 1 , wherein the plurality of control signals includes a phase locked loop (PLL) control signal, a frequency division control signal, a stop control signal, and a clock selecting signal.

16. A semiconductor apparatus comprising: a circuit including a predetermined function; a power control circuit that outputs: a power control signal to the circuit, and a signal that indicates when the power control signal is being supplied to the circuit; and a notification signal generating circuit, coupled to the power control circuit, that generates a notification signal for notifying a power supply apparatus when the power control signal is being supplied to the circuit based on the signal.

17. The semiconductor apparatus according to claim 16 , wherein a power supply voltage supplied to the circuit is adjusted according to the notification signal.

18. The semiconductor apparatus according to claim 16 , wherein the power control circuit comprises a state machine having a plurality of states including a power supply process state, and the signal is output during the power supply process state.

19. The semiconductor apparatus according to claim 18 , wherein the notification signal generating circuit generates the notification signal in a period when the state machine performs a process to supply the power to the circuit.

20. The semiconductor apparatus according to claim 18 , wherein the plurality of states includes a power stop state and an idle state.

21. A system comprising: a semiconductor apparatus comprising; a circuit including a predetermined function; a clock generating circuit that generates a clock signal supplied to the circuit; a clock control circuit that controls the clock generating circuit and outputs: a plurality of clock control signals to the clock generating circuit, a first signal that indicates when a frequency of the clock signal is being changed from a predetermined frequency to a higher frequency, and a second signal that indicates when the clock signal is being supplied to the circuit; a power control circuit that outputs: a power control signal to the circuit, and a third signal that indicates when the power control signal is being supplied to the circuit; and a notification signal generating circuit, coupled to the clock control circuit and the power control circuit, that generates a notification signal for notifying when the clock signal frequency is being changed based on the first signal, when the clock signal is being supplied to the circuit based on the second signal, and when the power control signal is being supplied to the circuit based on the third signal; and an output terminal, coupled to the notification signal generating circuit, for providing the notification signal; and a power supply apparatus, including an input terminal coupled to the output terminal, that supplies power to the semiconductor apparatus based on the notification signal.

22. The system according to claim 21 , wherein the power supply apparatus increases a voltage of the power supplied to the semiconductor apparatus when a signal in an active state is supplied as the notification signal.