Bus Transaction Monitoring and Debugging System Using FPGA

1. A bus transaction monitoring and debugging system, the system comprising: a first FPGA (Field Programmable Gate Array); a second FPGA; an application software; and a communication interface to connect the second FPGA with the application software; a TAP interface module to sense a change in a plurality of data signals and capture the change in the plurality of data signals; wherein the second FPGA comprises: a monitor RTL (Register Transfer Level) for tapping the plurality of data signals from different levels of the first FPGA; a transaction based signal trigger for capturing the plurality of signals tapped at different levels of the monitor RTL; a monitor data interface for storing a plurality of data signals of interest, and wherein the plurality of data signals of interest are selected and captured based on a user-defined set of instructions; and a data packet for converting the plurality of signals to a plurality of packets and transmit the plurality of packets to the application software; an application layer for providing an information regarding each bit to a monitor data interface to report an application algorithm regarding an availability of the data, and wherein the application layer includes a control register interface through which bit positions of the plurality of data signals are intimated to the data packetizer; a monitor register interface for storing the bit positions of the plurality of data signals; wherein the application software decodes the plurality of transmitted packets and displays the transaction on a waveform viewer by communicating an information related to the packets using a plurality of communication protocols, and wherein the waveform viewer is an Electronic design Automation (EDA) waveform viewer for displaying the plurality of data signals of interest.

2. The system of claim 1 , wherein the first FPGA is a device under test adapted for implementing a user logic.

3. The system of claim 1 , wherein the application software is adapted to interact with the EDA waveform viewer.

4. The system of claim 1 , wherein the application software provides a graphical user interface (GUI) to select a plurality of data signals and integrate the TAP interface in a user RTL.

5. The system of claim 1 , wherein the TAP interface module is provided with a 32-bit bus for transferring a data along with a FIFO control and a monitor control signals.

6. The system of claim 1 , wherein the monitor RTL includes: a signal sampling clock generator for generating a plurality of clock signals; a transaction monitor state machine for processing the plurality of data signals; a register interface for communicating bit positions of the plurality of data signals; the transaction based signal trigger and a transaction based bus trigger for forming a control mechanism; and a signal storage memory for storing the plurality of data signals after an occurrence of required conditions; wherein the control mechanism is formed on a basis of transaction start/end time.

7. The system of claim 1 , wherein the application software includes an algorithm which allows a user to select the plurality of data signals or interest in a USER DUT and brings out to the specific pins on the first FPGA by auto stitching of a TAP interface logic with a USER DUT RTL.

8. The system of claim 7 , wherein the algorithm is adapted to: generate a relevant information for the second FPGA which is loaded through a control register interface; programming the first FPGA and the second FPGA with relevant bit files once the bit file of the first FPGA is ready; and loading a trigger control information to the monitor RTL through the control register interface after programming the first FPGA and the second FPGA.

9. A method of providing a bus transaction monitoring and debugging, the method comprises steps of: tapping a plurality of data signals from different levels of a USER DUT RTL (register transfer logic); capturing the plurality of data signals tapped from the different levels of the USER DUT RTL; transmitting the captured plurality of data signals to a monitor RTL; processing the captured plurality of data signals by the monitor RTL; capturing a plurality of data signals of interest based on an occurrence of a user-defined set of instructions; converting the plurality of data signals of interest into a plurality of data packets by a data packetizer; transmitting the plurality of data packets to an application software through a communication interface; monitoring the plurality of data signals transmitted and decoding the plurality of data packets by the application software; and displaying a targeted transactions corresponding to details of the plurality of data signals, and wherein the details of the plurality of data signals are extracted from the decoded plurality of data packets on an Electronic Data Automation (EDA) waveform viewer.

10. The method of claim 9 , wherein capturing a plurality of data signals of interest based on a user-defined set of instructions comprises: generating a control mechanism in a transaction based signal trigger of the monitor RTL; loading a bit positions of the plurality of data signals from a register interface of the monitor RTL; and capturing the plurality of data signals in a signal store memory based on an activity in the plurality of data signals, when a user-defined conditions are met on the monitor RTL.

11. The method of claim 9 , wherein the step of transmitting the plurality of data packets to an application software running, comprising steps of: programming a first FPGA with a relevant bit files; programming a second FPGA with the relevant bit files; loading a trigger information into a monitor through a control register interface; programming a specification of pins and a functionality to the monitor through the control register interface; and feeding transaction details on a particular signal to the monitor.

12. The method of claim 9 , wherein the application software decodes the plurality of data packets based on an information regarding a bit correspondence and associates a signal name with each signal in the captured plurality of data signals such that appropriate signals are mapped with respective names in a waveform data to a waveform viewer.