Legal claims defining the scope of protection, as filed with the USPTO.
1. A data writing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units, each of the physical erasing units comprises a plurality of physical programing units, and the physical erasing units are grouped into at least a data area, the data writing method comprising: configuring a plurality of logical addresses to map to the physical erasing units in the data area; grouping at least one physical erasing unit among the physical erasing units besides the physical erasing units in the data area into a first buffer area; and grouping at least one physical erasing unit among the physical erasing units besides the physical erasing units in the data area into a second buffer area, wherein the at least one physical erasing unit of the first buffer area is different from the at least one physical erasing unit of the second buffer area; receiving a first write command, wherein the first write command instructs to write a first data to a first logical address among the logical addresses; determining whether a quantity of the first data is smaller than a predetermined value; if the quantity of the first data is smaller than the predetermined value, writing the first data into the at least one physical erasing unit of the first buffer area or the at least one physical erasing unit of the second buffer area; and if the first data is written into the at least one second physical erasing unit of the second buffer area, obtaining at least one second logical address mapped to at least one first physical programing unit in the at least one first physical erasing unit of the first buffer area, and copying merging valid data belonging to the at least one second logical address into a third physical erasing unit among the physical erasing units, wherein the number of the at least one second logical address is smaller than a merging threshold number and the third physical erasing unit is different from the at least one physical erasing unit of the first buffer area and the at least one physical erasing unit of the second buffer area.
2. The data writing method according to claim 1 , wherein the step of grouping the at least one physical erasing unit among the physical erasing units into the first buffer area and grouping the at least one physical erasing unit among the physical erasing units into the second buffer area comprises: setting up a first pointer and a second pointer, and pointing the first pointer and the second pointer at one of the physical programing units in the at least one physical erasing unit of the first buffer area or the at least one physical erasing unit of the second buffer area.
3. The data writing method according to claim 2 , wherein the step of writing the first data into the at least one physical erasing unit of the first buffer area or the at least one physical erasing unit of the second buffer area if the quantity of the first data is smaller than the predetermined value comprises: writing the first data into a second physical programing unit pointed by the second pointer; and moving the second pointer to a third physical programing unit, wherein programming sequence of the third physical programing unit follows the second physical programing unit.
4. The data writing method according to claim 2 , wherein the step of obtaining the at least one second logical address mapped to the at least one first physical programing unit in the at least one physical erasing unit of the first buffer area if the first data is written into the at least one physical erasing unit of the second buffer area comprises: obtaining the at least one first physical programing unit according to a physical programing unit pointed by the first pointer; and moving the first pointer to a fourth physical programing unit, and obtaining a third logical address mapped to the fourth physical programing unit.
5. The data writing method according to claim 4 , wherein the step of merging the valid data belonging to the at least one second logical address comprises: merging valid data belonging to the third logical address; and moving the first pointer to a fifth physical programing unit, wherein programming sequence of the fifth physical programing unit follows the fourth physical programing unit.
6. The data writing method according to claim 5 further comprising: after data in the fifth physical programing unit is merged, moving the first pointer to a sixth physical programing unit, wherein programming sequence of the sixth physical programing unit follows the fifth physical programing unit; and if the first pointer is pointed at a physical programing unit having last programming sequence in the first buffer area, determining whether the second pointer is pointed at a physical programing unit having last programming sequence in the second buffer area, and if the second pointer is pointed at the physical programing unit having the last programming sequence in the second buffer area, moving the first pointer to a physical programing unit having first programming sequence in the second buffer area.
7. The data writing method according to claim 1 , wherein the predetermined value is a size of one of the physical programing units.
8. The data writing method according to claim 1 , wherein a size of the first buffer area is equal to a size of the second buffer area.
9. A memory storage device, comprising: a connector, configured to couple to a host system; a rewritable non-volatile memory module, comprising a plurality of physical erasing units, wherein each of the physical erasing units comprises a plurality of physical programming units, and the physical erasing units are grouped into at least a data area; and a memory controller, coupled to the connector and the rewritable non-volatile memory module, wherein the memory controller is configured to configure a plurality of logical addresses to map to the physical erasing units in the data area, group at least one physical erasing unit among the physical erasing units besides the physical erasing units in the data area into a first buffer area, and group at least one physical erasing unit among the physical erasing units besides the physical erasing units in the data area into a second buffer area, wherein the at least one physical erasing unit of the first buffer area is different from the at least one physical erasing unit of the second buffer area, wherein the memory controller is configured to receive a first write command, wherein the first write command instructs to write a first data to a first logical address among the logical addresses, and the memory controller determines whether a quantity of the first data is smaller than a predetermined value, if the quantity of the first data is smaller than the predetermined value, the memory controller is configured to write the first data into the at least one physical erasing unit of the first buffer area or the at least one physical erasing unit of the second buffer area, if the memory controller writes the first data into the at least one second physical erasing unit of the second buffer area, the memory controller is configured to obtain at least one second logical address mapped to at least one first physical programing unit in the at least one physical erasing unit of the first buffer area and copy valid data belonging to the at least one second logical address into a third physical erasing unit among the physical erasing units, wherein the number of the at least one second logical address is smaller than a merging threshold number and the third physical erasing unit is different from the at least one physical erasing unit of the first buffer area and the at least one physical erasing unit of the second buffer area.
10. The memory storage device according to claim 9 , wherein the memory controller is further configured to set up a first pointer and a second pointer and point the first pointer and the second pointer at one of the physical programing units in the at least one physical erasing unit of the first buffer area or the at least one physical erasing unit of the second buffer area.
11. The memory storage device according to claim 10 , wherein if the quantity of the first data is smaller than the predetermined value, the memory controller is further configured to write the first data into a second physical programing unit pointed by the second pointer and move the second pointer to a third physical programing unit, wherein programming sequence of the third physical programing unit follows the second physical programing unit.
12. The memory storage device according to claim 10 , wherein the memory controller is further configured to obtain the at least one first physical programing unit according to a physical programing unit pointed by the first pointer, move the first pointer to a fourth physical programing unit, and obtain a third logical address mapped to the fourth physical programing unit.
13. The memory storage device according to claim 12 , wherein the memory controller is further configured to merge valid data belonging to the third logical address and move the first pointer to a fifth physical programing unit, wherein programming sequence of the fifth physical programing unit follows the fourth physical programing unit.
14. The memory storage device according to claim 13 , wherein after data in the fifth physical programing unit is merged, the memory controller is further configured to move the first pointer to a sixth physical programing unit, wherein programming sequence of the sixth physical programing unit follows the fifth physical programing unit, if the first pointer is pointed at a physical programing unit having last programming sequence in the first buffer area, the memory controller is further configured to determine whether the second pointer is pointed at a physical programing unit having last programming sequence in the second buffer area, and if the second pointer is pointed at the physical programing unit having the last programming sequence in the second buffer area, the memory controller is further configured to move the first pointer to a physical programing unit having first programming sequence in the second buffer area.
15. The memory storage device according to claim 9 , wherein the predetermined value is a size of one of the physical programing units.
16. The memory storage device according to claim 9 , wherein a size of the first buffer area is equal to a size of the second buffer area.
17. A memory controller, for controlling a rewritable non-volatile memory module, the memory controller comprising: a host interface, configured to couple to a host system; a memory interface, configured to couple to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units, each of the physical erasing units comprises a plurality of physical programing units, and the physical erasing units are grouped into at least a data area; and a memory management circuit, coupled to the host interface and the memory interface, wherein the memory management circuit is configured to configure a plurality of logical addresses to map to the physical erasing units in the data area, group at least one physical erasing unit among the physical erasing units besides the physical erasing units in the data area into a first buffer area, and group at least one physical erasing unit among the physical erasing units besides the physical erasing units in the data area into a second buffer area, wherein the at least one physical erasing unit of the first buffer area is different from the at least one physical erasing unit of the second buffer area, wherein the memory management circuit is configured to receive a first write command, wherein the first write command instructs to write a first data to a first logical address among the logical addresses, and the memory management circuit is configured to determine whether a quantity of the first data is smaller than a predetermined value, if the quantity of the first data is smaller than the predetermined value, memory management circuit is configured to write the first data into the at least one physical erasing unit of the first buffer area or the at least one physical erasing unit of the second buffer area, if the memory management circuit writes the first data into the at least one physical erasing unit of the second buffer area, the memory management circuit obtains at least one second logical address mapped to at least one first physical programing unit in the at least one physical erasing unit of the first buffer area and copies merges valid data belonging to the at least one second logical address into a third physical erasing unit among the physical erasing units, wherein the number of the at least one second logical address is smaller than a merging threshold number and the third physical erasing unit is different from the at least one physical erasing unit of the first buffer area and the at least one physical erasing unit of the second buffer area.
18. The memory controller according to claim 17 , wherein the memory management circuit is further configured to set up a first pointer and a second pointer and points the first pointer and the second pointer at one of the physical programing units in the at least one physical erasing unit of the first buffer area or the at least one physical erasing unit of the second buffer area.
19. The memory controller according to claim 18 , wherein if the quantity of the first data is smaller than the predetermined value, the memory management circuit is further configured to write the first data into a second physical programing unit pointed by the second pointer and moves the second pointer to a third physical programing unit, wherein programming sequence of the third physical programing unit follows the second physical programing unit.
20. The memory controller according to claim 18 , wherein the memory management circuit is further configured to obtain the at least one first physical programing unit according to a physical programing unit pointed by the first pointer, move the first pointer to a fourth physical programing unit, and obtain a third logical address mapped to the fourth physical programing unit.
21. The memory controller according to claim 20 , wherein the memory management circuit is further configured to merge valid data belonging to the third logical address and moves the first pointer to a fifth physical programing unit, wherein programming sequence of the fifth physical programing unit follows the fourth physical programing unit.
22. The memory controller according to claim 21 , wherein after data in the fifth physical programing unit is merged, the memory management circuit is further configured to move the first pointer to a sixth physical programing unit, wherein programming sequence of the sixth physical programing unit follows the fifth physical programing unit, if the first pointer is pointed at a physical programing unit having last programming sequence in the first buffer area, the memory management circuit is further configured to determine whether the second pointer is pointed at a physical programing unit having last programming sequence in the second buffer area, and if the second pointer is pointed at the physical programing unit having the last programming sequence in the second buffer area, the memory management circuit is further configured to move the first pointer to a physical programing unit having first programming sequence in the second buffer area.
23. The memory controller according to claim 17 , wherein the predetermined value is a size of one of the physical programing units.
24. The memory controller according to claim 17 , wherein a size of the first buffer area is equal to a size of the second buffer area.
Unknown
November 3, 2015
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