Smart Bridge for Memory Core

1. An apparatus comprising: a first semiconductor die including a three-dimensional (3D) memory that includes multiple memory cells arranged in multiple physical levels that are monolithically formed above a substrate, wherein the 3D memory further includes circuitry associated with operation of the multiple memory cells; a second semiconductor die including a memory device interface and a memory controller interface, wherein the second semiconductor die is coupled to the first semiconductor die via the memory device interface; and a third semiconductor die that includes a memory controller of the 3D memory, wherein the third semiconductor die includes a host interface, a memory interface, a processor, and an error correction coding (ECC) engine, wherein the host interface is configured to enable communication with a host device, and wherein the memory interface is coupled to the memory controller interface of the second semiconductor die, wherein the memory device interface and the memory controller interface of the second semiconductor die are configured to enable communication of data and control information between the memory controller and the 3D memory.

2. The apparatus of claim 1 , wherein the second semiconductor die includes a charge pump and wherein the 3D memory does not include a charge pump, and wherein the second semiconductor die further includes a second ECC engine.

3. The apparatus of claim 1 , wherein the substrate is a silicon substrate.

4. The apparatus of claim 1 , wherein the circuitry associated with operation of the multiple memory cells is configured to be responsive to a write instruction to store data into memory cells of the 3D memory and to be responsive to a read instruction to read data from the memory cells of the 3D memory.

5. The apparatus of claim 2 , wherein the second semiconductor die includes multi-ported static random access memory.

6. The apparatus of claim 5 , wherein the second semiconductor die includes circuitry configured to concurrently process multiple word lines of data at the multi-ported static random access memory.

7. The apparatus of claim 6 , wherein the circuitry of the second semiconductor die is configured to process the multiple word lines of data from the 3D memory to detect at least one of an interference condition, a program disturb condition, and a read disturb condition.

8. The apparatus of claim 6 , wherein the multiple word lines of data correspond to a single word line read with different sets of read voltages, and wherein the second ECC engine of the second semiconductor die is configured to perform error correction processing of the multiple word lines of data.

9. The apparatus of claim 6 , wherein the circuitry of the second semiconductor die is configured to process the multiple word lines of data to detect specific data patterns.

10. The apparatus of claim 6 , wherein the circuitry of the second semiconductor die is configured to process the multiple word lines of data to scramble data to be stored to the 3D memory.

11. The apparatus of claim 6 , wherein the circuitry of the second semiconductor die is configured to operate the multi-ported static random access memory as a cache memory.

12. The apparatus of claim 11 , wherein the second semiconductor die includes a test engine configured to test an operation of the 3D memory.

13. The apparatus of claim 12 , further comprising a fourth semiconductor die including a NAND flash memory, wherein the second semiconductor die includes a second memory device interface coupled to the NAND flash memory.

14. The apparatus of claim 13 , wherein the second ECC engine is configured to encode first data to be stored in the 3D memory, and wherein the second semiconductor die includes a third ECC engine configured to encode second data to be stored in the NAND flash memory.