Semiconductor Memory Device

1. A semiconductor memory device reading data in units of page, the device comprising: a memory cell array configured to hold data multiplexed in at least three pages; a plurality of latch circuits configured to read and hold the multiplexed data at a startup; and an arithmetic operation circuit configured to perform operations by use of the multiplexed data.

2. The device according to claim 1 , wherein the operation is a majority logic operation.

3. The device according to claim 1 , wherein the memory cell array includes a plurality of memory cells associated with rows and columns, the page includes a plurality of memory cells arranged on the same row, and the data is multiplexed in a column direction.

4. The device according to claim 1 , wherein the plural latch circuits include first to third latch circuits, the data is multiplexed in first to third pages, first data read from the first page is stored in the third latch circuit at the startup, second data read from the second page is stored in the first latch circuit, a logical OR operation result of the first data and second data is stored in the second latch circuit, a logical AND operation result of the first data and second data is stored in the third latch circuit, third data read from the third page is stored in the first latch circuit, a logical AND operation result of the third data and the logical OR operation result is stored in the second latch circuit, and a logical OR operation result of a logical AND operation result of the first data and second data and a logical AND operation result of the third data and the logical OR operation result is stored in the third latch circuit.

5. The device according to claim 1 , wherein the multiplexed data items are multiplexed in each page.

6. The device according to claim 5 , wherein the multiplexed data includes substantial data and complementary data in each page.

7. The device according to claim 1 , wherein the memory cell array includes a plurality of string units which are a set of a plurality of NAND strings each including first and second selection transistors and a plurality of memory cells serially connected between the first and second selection transistors, and at least two pages among the three pages which hold the multiplexed data are allocated to different ones of the string units.

8. The device according to claim 7 , wherein at least one different string unit is inserted between the two string units to which at least two pages of the three pages are allocated.

9. The device according to claim 1 , wherein the memory cell array includes: a plurality of string units which are a set of a plurality of NAND strings each including first and second selection transistors and a plurality of memory cells serially connected between the first and second selection transistors, and a plurality of word lines each of which commonly connects plural ones of the memory cells, at least one page is allocated to the plural memory cells connected to the same word line in the string unit, and at least two pages of the three pages which hold the multiplexed data are allocated to different word lines.

10. The device according to claim 9 , wherein at least one different word line is inserted between two word lines to which at least two pages of the three pages are allocated.

11. The device according to claim 9 , wherein the plural word lines are stacked above a semiconductor substrate.

12. The device according to claim 1 , wherein the memory cell array includes a plurality of memory cells three-dimensionally stacked above a semiconductor substrate.

13. The device according to claim 1 , wherein the multiplexed data is ROM fuse information.

14. A method for reading data from a semiconductor memory device which stores data multiplexed in a plurality of pages, the method comprising: reading first data of the multiplexed data from a first page at a startup; reading second data of the multiplexed data from a second page after the first data is read; reading third data of the multiplexed data from a third page after the second data is read; and performing an operation by use of the first to third data to determine contents of the multiplexed data.

15. The method according to claim 14 , wherein the operation is a majority logic operation for bits of the first to third data.

16. The method according to claim 14 , wherein the semiconductor memory device has a plurality of memory cells three-dimensionally stacked above a semiconductor substrate.

17. The method according to claim 14 , wherein the multiplexed data is ROM fuse information.

18. The device according to claim 1 , wherein the arithmetic operation circuit determines a single data from the multiplexed data.

19. The device according to claim 18 , wherein at least a part of the single data is for use as parameter data for the semiconductor memory device.

20. The device according to claim 19 , wherein the single data has a size of the page.

21. The method according to claim 14 , wherein the performing an operation includes determining a single data from the multiplexed data.

22. The method according to claim 21 , wherein at least a part of the single data is for use as parameter data for the semiconductor device.

23. The method according to claim 22 , wherein the single data has a size of each of the pages.