Copy-On-Write Buffer For Restoring Program Code From A Speculative Region To A Non-Speculative Region

1. A processor, comprising: an instruction execution pipeline comprising a re-order buffer, register renaming circuitry and a register alias table, said register alias table to hold entries to correlate logical registers to physical registers, each of said entries having space to indicate whether its logical register to physical register correlation existed during a transition from a non speculative region of code to a speculative region of code, said speculative region of code capable of extending beyond a size of said re-order buffer such that architectural state is written to during extended speculative execution, said instruction execution pipeline having logic circuitry to perform the following upon retirement of an overwriter instruction of a logical register having an entry in said register alias table: enter an identifier of a physical register correlated to said logical register into a free list if said entry does not indicate existence of said entry during a non-speculative code to speculative code transition, said physical register freely useable after placement of its identifier into said free list; enter an identifier of a physical register correlated to said logical register into a store if said entry indicates existence of said entry during a non-speculative code to speculative code transition, said physical register not being freely useable after placement of its identifier into said store, said identifier of said physical register and an identifier of said logical register to be moved from said store back into said register alias table upon roll-back of extended speculative code execution to the end of non-speculative code execution.

2. The processor of claim 1 wherein during extended speculative execution branches are resolved before they retire in traditional speculative execution within said re-order buffer's size.

3. The processor of claim 1 wherein speculative branches are permitted to commit to architectural state during extended speculative execution.

4. The processor of claim 1 wherein the instruction execution pipeline performs the following if extended speculative execution is deemed unsuccessful: clearing state of traditional speculative execution from said pipeline including clearing contents of said re-order buffer determined from said traditional speculative execution; clearing entries of said register alias table that do not indicate existence during a transition from non-speculative to speculative code regions and keeping entries in said register alias table that indicate existence during transition from non-speculative to speculative code regions; moving entries in said store to said register alias table.

5. The processor of claim 1 wherein the instruction execution pipeline performs the following as part of a transition from non-speculative to speculative regions of code: stores program control content from control register space into temporary register space; creates an entry in said register alias table for said temporary register space that indicates existence of said entry during transition from non-speculative to speculative regions of code.

6. The processor of claim 5 wherein said instruction execution pipeline moves said program control content from said temporary register space to said control register space upon failure of extended speculation.

7. The processor of claim 5 wherein said entry in said register alias table for said temporary register space is moved to said store if said temporary register space is overwritten during execution of extended speculation.

8. The processor of claim 5 wherein said entry is moved back into said register alias table upon failure of said extended speculation.

9. The processor of claim 5 wherein said control register space at least includes an MXCSR register.

10. The processor of claim 1 wherein the instruction execution pipeline performs the following as part of a transition from non-speculative to speculative regions of code: combines a portion of a first register having reserved space in a second register into said second register; creates an entry in said register alias table for said second register that indicates existence of said entry during transition from non-speculative to speculative regions of code.

11. The processor of claim 10 wherein said reserved space is AH space and said second register is a RAX register.

12. The processor of claim 10 wherein said instruction execution pipeline stores said portion back into said first register upon failure of extended speculative execution.

13. The processor of claim 10 wherein said instruction execution pipeline keeps said portion in said second register upon failure of extended speculative execution.

14. The processor of claim 10 wherein said processor stores a first entry in said store for said portion if said portion is separately overwritten during execution of extended speculation and stores a second entry in said store for said second register if said second register is separately overwritten during execution of extended speculation.

15. The processor of claim 1 wherein said free list is managed with logic circuitry in a data fetch stage of said instruction execution pipeline.

16. The processor of claim 1 wherein said register alias table is located in a data fetch stage of said instruction execution pipeline.

17. The processor of claim 1 wherein said register alias table is located in a write back stage of said instruction execution pipeline, said instruction execution pipeline also having another register alias table in a data fetch stage of said instruction execution pipeline, said another register alias table to track logical to physical register correlations during renaming, said register alias table to track logical to physical register correlations representing retired in order program state.

18. A processor, comprising: an instruction execution pipeline comprising a re-order buffer, register renaming circuitry, a register alias table and a register reclaim table, said register reclaim table to include entries identifying physical registers that previously allocated in the register alias table but for whom , for each of said physical registers, an overwriter of a logical register correlated to a physical register has allocated but not retired, each of said entries having space to indicate whether its physical register existed during a transition from a non speculative region of code to a speculative region of code, said speculative region of code capable of extending beyond a size of said re-order buffer such that architectural state is written to during extended speculative execution, said instruction execution pipeline having logic circuitry to perform the following upon retirement of an overwriter instruction of a logical register having an entry in said register reclaim table: enter an identifier of a physical register correlated to said logical register into a free list if said entry does not indicate existence of said entry during a non-speculative code to speculative code transition, said physical register freely useable after placement of its identifier into said free list; enter an identifier of a physical register correlated to said logical register into a store if said entry indicates existence of said entry during a non-speculative code to speculative code transition, said physical register not being freely useable after placement of its identifier into said store, said identifier of said physical register to be moved from said store back into said register alias table upon roll-back of extended speculative code execution to the end of non-speculative code execution.

19. The processor of claim 18 wherein said identifier of said physical register is moved from said register alias table to said register reclaim table upon allocation of said logical register's overwriter into said register alias table.

20. The processor of claim 19 wherein said register alias table has entries to correlate logical registers to physical registers, each of said entries having space to indicate whether its logical register to physical register correlation existed during a transition from a non speculative region of code to a speculative region of code, wherein, when a physical register identifier is moved from said register alias table to said register reclaim table, its associated indication of whether its logical register to physical register correlation existed during a transition from a non speculative region of code to a speculative region of code is also moved from said register alias table to said register reclaim table.

21. A processor, comprising: an instruction execution pipeline comprising a re-order buffer, register renaming circuitry, a register alias table, a first register reclaim table and a second register reclaim table, both of said register reclaim tables to include entries identifying physical registers that previously allocated in the register alias table but for whom, for each of said physical registers, an overwriter of a logical register correlated to a physical register has allocated but not retired, said instruction execution pipeline capable of executing over a speculative code region that extends beyond a size of said re-order buffer such that architectural state is written to during extended speculative execution, said instruction execution pipeline having logic circuitry to perform the following: create a first entry in said first register reclaim table for a first overwriter instruction, said first overwriter instruction to overwrite a first logical register that has a corresponding physical register that was not allocated for in said register alias table during a transition from non speculative code to speculative code, said first physical register being freely useable upon retirement of said first overwriter instruction; create a second entry in said second register reclaim table for a second overwriter instruction, said second overwriter instruction to overwrite a second logical register that has a corresponding second physical register that was allocated for in said register alias table during a transition from non speculative code to speculative code, said second physical register not being freely useable upon retirement of said second overwriter instruction, wherein, an identifier of said second physical register is moved into said register alias table upon roll-back of extended speculative code execution to the end of non-speculative code execution.

22. The processor of claim 21 wherein said first register reclaim table is kept in a structure that also keeps a freelist.

23. The processor of claim 21 wherein an identifier of said second physical register is moved from said second register reclaim table to a store upon retirement of said second overwriter instruction, wherein, said identifier of said physical register is moved from said store into said register alias table upon roll-back of extended speculative code execution to the end of non-speculative code execution.

24. The processor of claim 23 wherein said second register reclaim table and said store are kept in a same structure.

25. The processor of claim 24 wherein said instruction execution pipeline supports extended speculative execution for integer registers but not floating point registers.

26. A processor, comprising: an instruction execution pipeline comprising a table to hold entries that correlate logical registers to physical registers, said entries having space to indicate whether its logical register to physical register correlation existed during a transition from a non speculative region of code to a speculative region of code, said instruction execution pipeline having a write back stage to write architectural state during extended speculative execution, said instruction execution pipeline having a re-order buffer, said extended speculative execution capable of extending beyond a size of said re-order buffer.

27. The processor of claim 26 wherein said instruction execution pipeline has logic circuitry to perform the following upon retirement of an overwriter instruction of a logical register having an entry in said table: enter an identifier of a physical register correlated to said logical register into a free list if said entry does not indicate existence of said entry during a non-speculative code to speculative code transition, said physical register freely useable after placement of its identifier into said free list.

28. The processor of claim 26 where said instruction execution pipeline has logic circuitry to perform the following upon retirement of an overwriter instruction of a logical register having an entry in said table: enter an identifier of a physical register correlated to said logical register into a store and not a free list if said entry indicates existence of said entry during a non-speculative code to speculative code transition, said physical register not being freely useable after placement of its identifier into said store.