Legal claims defining the scope of protection, as filed with the USPTO.
1. A computer implemented method for generating an ordered sequence from a predetermined sequence of symbols using semaphore protected interleaved caches, the method comprising: dividing the predetermined sequence of symbols into two or more interleaved caches; mapping each of the two or more interleaved caches to a particular semaphore of a group of semaphores; storing the group of semaphores into a shared memory, the shared memory accessible by a plurality of session processes; and granting access to one of the two or more interleaved caches only after one of the plurality of session processes performs a semaphore altering read-modify-write operation on the particular semaphore.
2. The method of claim 1 , wherein the predetermined sequence of symbols is a sequence of successive integers.
3. The method of claim 1 , wherein the predetermined sequence of symbols is determined algorithmically using a sequence object.
4. The method of claim 1 , wherein the predetermined sequence of symbols is divided into a two or more interleaved caches using an interleave rank value.
5. The method of claim 1 , wherein the predetermined sequence of symbols is assigned into a two or more interleaved caches uses a round-robin assignment.
6. The method of claim 1 , wherein storing the group of semaphores into a shared memory comprises storing two or more semaphores into contiguous bits in a machine word.
7. The method of claim 1 , wherein storing the group of semaphores into a shared memory comprises storing two or more semaphores into contiguous machine words in an array.
8. A computer system to generating ordered sequences using semaphore protected interleaved caches, comprising: a computer processor to execute a set of program code instructions; and a memory to hold the program code instructions, in which the program code instructions comprises program code to perform: dividing the predetermined sequence of symbols into two or more interleaved caches; mapping each of the two or more interleaved caches to a particular semaphore of a group of semaphores; storing the group of semaphores into a shared memory, the shared memory accessible by a plurality of session processes; and granting access to one of the two or more interleaved caches only after one of the plurality of session processes performs a semaphore altering read-modify-write operation on the particular semaphore.
9. The computer system of claim 8 , wherein the predetermined sequence of symbols is a sequence of successive integers.
10. The computer system of claim 8 , wherein the predetermined sequence of symbols is determined algorithmically using a sequence object.
11. The computer system of claim 8 , wherein the predetermined sequence of symbols is divided into a two or more interleaved caches using an interleave rank value.
12. The computer system of claim 8 , wherein the predetermined sequence of symbols is assigned into a two or more interleaved caches uses a round-robin assignment.
13. The computer system of claim 8 , wherein storing the group of semaphores into a shared memory comprises storing two or more semaphores into contiguous bits in a machine word.
14. The computer system of claim 8 , wherein storing the group of semaphores into a shared memory comprises storing two or more semaphores into contiguous machine words in an array.
15. A computer program product embodied in a non-transitory computer readable medium, the computer readable medium having stored thereon a sequence of instructions which, when executed by a processor causes the processor to execute a method to implement generating ordered sequences using semaphore protected interleaved caches, the method comprising: dividing the predetermined sequence of symbols into two or more interleaved caches; mapping each of the two or more interleaved caches to a particular semaphore of a group of semaphores; storing the group of semaphores into a shared memory, the shared memory accessible by a plurality of session processes; and granting access to one of the two or more interleaved caches only after one of the plurality of session processes performs a semaphore altering read-modify-write operation on the particular semaphore.
16. The computer program product of claim 15 , wherein the predetermined sequence of symbols is a sequence of successive integers.
17. The computer program product of claim 15 , wherein the predetermined sequence of symbols is determined algorithmically using a sequence object.
18. The computer program product of claim 15 , wherein the predetermined sequence of symbols is divided into a two or more interleaved caches using an interleave rank value.
19. The computer program product of claim 15 , wherein the predetermined sequence of symbols is assigned into a two or more interleaved caches uses a round-robin assignment.
20. The computer program product of claim 15 , wherein storing the group of semaphores into a shared memory comprises storing two or more semaphores into contiguous bits in a machine word.
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November 17, 2015
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