Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of displaying data, comprising: detecting, at a timing generator, an assertion of a data ready signal in a display pipeline, the display pipeline having access to a shared system resource that is accessed by a plurality of devices, wherein the data ready signal indicates the availability of the shared system resource and the readiness of a line of display data for transmission from the display pipeline; and generating, by the timing generator, a line-transmit signal based upon a clock signal and the asserted data ready signal, wherein the line-transmit signal is provided to the display pipeline and indicates that the display pipeline should transmit the line of display data.
2. The method of claim 1 , wherein the line-transmit signal is substantially coincident with the clock signal when the data ready signal is asserted.
3. The method of claim 1 , wherein the line-transmit signal is delayed with respect to the clock signal when the data ready signal is not asserted.
4. The method of claim 1 , further comprising: determining the availability of the line of display data for transmission; and asserting the data ready signal when the line of display data is available for transmission.
5. The method of claim 4 , wherein the determining the availability of the line of display data for transmission comprises: retrieving the line of display data from a memory.
6. The method of claim 5 , wherein determining the availability of the line of display data for transmission further comprises: processing the line of display data before said asserting the data ready signal.
7. The method of claim 4 , wherein the asserting the data ready signal includes: signaling on a dedicated wire from the display pipeline.
8. The method of claim 4 , wherein the asserting the data ready signal includes: transmitting a message from the display pipeline.
9. The method of claim 4 , wherein the asserting the data ready signal includes: modifying a predetermined register, wherein the predetermined register represents the data ready signal.
10. The method of claim 1 , wherein the display pipeline is configured to de-assert the data ready signal.
11. The method of claim 1 , wherein a timing generator is configured to de-assert the data ready signal after generating the line-transmit signal.
12. The method of claim 1 , wherein the detecting the assertion of the data ready signal further comprises: transitioning to a waiting mode when the assertion of the data ready signal is not detected.
13. The method of claim 12 , wherein the waiting mode further comprises: checking periodically for the assertion of the data ready signal during the waiting mode.
14. The method of claim 13 , further comprising: transitioning out of the waiting mode after a predetermined time interval elapses.
15. An apparatus, comprising: a display pipeline configured to assert a data ready signal, the display pipeline having access to a shared system resource that is accessed by a plurality of devices, wherein the data ready signal indicates the availability of the shared system resource and the readiness of a line of display data for transmission from the display pipeline; and a timing generator coupled to the display pipeline, and configured to generate a line-transmit signal based upon a clock signal and the data ready signal asserted by the display pipeline and indicates that the display pipeline should transmit the line of display data.
16. The apparatus of claim 15 , wherein the timing generator is further configured to delay the generation of the line-transmit signal if the data ready signal is not asserted.
17. The apparatus of claim 15 , wherein the display pipeline is further configured to transmit the line of display data out of the display pipeline upon receiving the line-transmit signal.
18. The apparatus of claim 15 , wherein the display pipeline is further configured to retrieve the line of display data from a memory, and to assert the data ready signal after the line of display data is retrieved from the memory.
19. The apparatus of claim 15 , wherein the display pipeline and the timing generator are located in a graphics processor card.
20. The apparatus of claim 15 , wherein the display pipeline is configured to de-assert the data ready signal.
21. The apparatus of claim 15 , wherein the timing generator is configured to de-assert the data ready signal after generating the line-transmit signal.
22. A non-transitory computer readable storage medium storing computer-executable instructions which, when executed, cause the transmission of a line of display data using a method comprising: detecting, at a timing generator, an assertion of a data ready signal in a display pipeline, the display pipeline having access to a shared system resource that is accessed by a plurality of devices, wherein the data ready signal indicates the availability of the shared system resource and the readiness of the line of display data for transmission from the display pipeline; and generating, by the timing generator, a line-transmit signal based upon a clock signal and the asserted data ready signal, wherein the line-transmit signal is provided to the display pipeline and indicates that the display pipeline should transmit the line of display data.
Unknown
November 17, 2015
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.