Point to Multi-Point Clock-Forwarded Signaling for Large Displays

1. A system for transmitting data, the system comprising: a transmitter comprising: a plurality of data output circuits to operate at a data rate; each of the plurality of data output circuits comprising a delay adjust circuit to delay a transmitted signal; and a sampling clock output circuit to output a sampling clock signal with a total sampling clock edge rate equal to the data rate; and a plurality of receivers, each of the plurality of receivers connected to a corresponding one of the plurality of data output circuits, each of the plurality of receivers comprising: a sampling clock input connected to the sampling clock output circuit; a data input circuit; and a receiver output wherein the delay adjust circuit of a data output circuit of the plurality of data output circuits comprises a phase interpolator.

2. The system of claim 1 , wherein the sampling clock inputs of the plurality of receivers are connected to the sampling clock output circuit by a sampling clock splitting tree.

3. The system of claim 2 , wherein the sampling clock splitting tree comprises a plurality of transmission line splitters, each of the plurality of transmission line splitters having an input at a first characteristic impedance and two outputs at a second characteristic impedance, the second characteristic impedance being twice the first characteristic impedance.

4. The system of claim 1 , wherein the sampling clock inputs of the plurality of receivers are connected to the sampling clock output circuit by a fly-by architecture.

5. The system of claim 1 , comprising a plurality of inductors, each of the plurality of inductors connected to the sampling clock input of one of the plurality of receivers.

6. The system of claim 1 , wherein the delay adjust circuit of one of the plurality of data output circuits is a variable delay line.

7. The system of claim 1 , wherein the delay adjust circuit of a data output circuit of the plurality of data output circuits is a phase interpolator.

8. The system of claim 1 , wherein the sampling clock output circuit comprises a phase locked loop.

9. The system of claim 1 , wherein the system is connected to perform a sweep calibration to set a delay in the delay adjust circuit.

10. The system of claim 9 , wherein the sweep calibration comprises: sending, by a data output circuit of the plurality of data output circuits, a sequence of alternating ones and zeros; operating a receiver of the plurality of receivers in a mode in which every other sampling clock edge is disregarded; changing the delay in the delay adjust circuit of the data output circuit in increments in a first direction until both, at a first threshold delay, a first pass-fail or fail-pass boundary is reached, and, at a second threshold delay, a second pass-fail or fail-pass boundary is reached; determining, from the first threshold delay and from the second threshold delay, a range of delays corresponding to a pass region; and setting the delay of the delay adjust circuit of the data output circuit to a value that is substantially centered in the pass region.

11. The system of claim 1 , wherein the system is connected to perform an incremental adjustment of a delay of the delay adjust circuit of one of the plurality of data output circuits, starting from an initial delay value.

12. The system of claim 11 , wherein the incremental adjustment of the delay comprises: sending, by a data output circuit of the plurality of data output circuits, a sequence of alternating ones and zeros; operating a receiver of the plurality of receivers in a mode in which every other sampling clock edge is disregarded; increasing the delay, in a first trial delay adjustment, to a value exceeding the initial delay value by an amount corresponding to 90 degrees of sampling clock phase; decreasing the delay, in a second trial delay adjustment, to a value less than the initial delay value by an amount corresponding to 90 degrees of sampling clock phase; setting the delay to a value exceeding the initial value by an increment when the second trial delay adjustment resulted in a transition at the receiver output of the receiver; and setting the delay to a value less than the initial delay value by the increment when the first trial delay adjustment resulted in a transition at the receiver output of the receiver.

13. A video display comprising the system of claim 1 , wherein the system is connected to perform a periodic incremental delay adjustment, starting from an initial delay value and wherein the system is connected to perform the periodic incremental delay adjustment during a blanking interval of the video display.

14. The system of claim 1 , wherein each of the plurality of receivers comprises a clocked comparator.

15. The system of claim 1 , wherein the delay adjust circuit is to be controlled by a digital signal.

16. The system of claim 15 , further comprising a back channel, connected to a receiver of the plurality of receivers and to the delay adjust circuit of a data output circuit of the plurality of data output circuits, to: measure a delay error in the receiver; and adjust a delay in the delay adjust circuit of the data output circuit, to reduce the delay error.

17. The system of claim 16 , wherein the back channel comprises a digital delay control output connected to the delay adjust circuit of the data output circuit corresponding to the receiver.

18. A method of adjusting a data signal delay, the method comprising: sending, by a data output circuit comprising a delay adjust circuit configured to delay a transmitted signal by the data signal delay, a sequence of alternating ones and zeros to an input of a receiver having a receiver output; sending, by a clock line driver, a sampling clock to the receiver; sampling, by the receiver, the sequence of alternating ones and zeros on every other edge of the sampling clock; changing the delay in the delay adjust circuit in increments in a first direction until both, at a first threshold delay, a first pass-fail or fail-pass boundary is reached, and, at a second threshold delay, a second pass-fail or fail-pass boundary is reached; determining, from the first threshold delay and from the second threshold delay, a range of delays corresponding to a pass region; and setting the data signal delay to a value that is substantially centered in the pass region.

19. The method of claim 18 , further comprising: increasing the delay, in a first trial delay adjustment, to a value exceeding an initial delay value by an amount corresponding to 90 degrees of sampling clock phase; decreasing the delay, in a second trial delay adjustment, to a value less than the initial delay value by an amount corresponding to 90 degrees of sampling clock phase; setting the data signal delay to a value exceeding the initial delay value by an increment when the second trial delay adjustment resulted in a transition at the receiver output; and setting the data signal delay to a value less than the initial delay value by the increment when the first trial delay adjustment resulted in a transition at the receiver output.