Glitchless Clock Switching That Handles Stopped Clocks

1. A method comprising: generating an output clock signal using one of a first clock signal and a second clock signal; receiving a transition of a select signal indicating to switch from generating the output clock signal using the one of the first clock signal and the second clock signal to generating the output clock signal using another of the first clock signal and the second clock signal; generating a first reset signal responsive to a direction of the transition of the select signal being in a first direction; generating a second reset signal responsive to the direction of the transition of the select signal being in a second direction; supplying the first reset signal to reset a first circuit forming a first path used by the first clock signal if the direction of the transition is in the first direction; and supplying the second reset signal to reset a second circuit forming a second path used by the second clock signal if the direction of the transition is in the second direction.

2. The method as recited in claim 1 wherein one of the first and second clock signals is inactive when the transition occurs.

3. The method as recited in claim 1 further comprising: generating the first reset signal using a filtered clock signal based on the second clock signal.

4. The method as recited in claim 3 further comprising filtering the second clock signal in a ripple counter to generate the filtered clock signal.

5. The method as recited in claim 1 further comprising: generating the second reset signal using a filtered clock signal based on the first clock signal.

6. The method as recited in claim 1 receiving the first and second clock signals at a multiplexer circuit and generating a multiplexer output according to the select signal.

7. The method as recited in claim 1 further comprising resampling the select signal.

8. The method as recited in claim 7 further comprising detecting an edge of the select signal.

9. The method as recited in claim 8 further comprising creating a first pulse based on a detected first edge of the select signal and using the first pulse as the first reset signal.

10. The method as recited in claim 8 further comprising creating a second pulse based on a detected second edge of the select signal and using the second pulse as the second reset signal.

11. The method as recited in claim 1 further comprising receiving the first and second clock signals and the select signal at input terminals of an integrated circuit and supplying the output clock signal from the integrated circuit.

12. An integrated circuit comprising: a glitchless switching circuit to generate an output clock signal from one of a first clock signal and a second clock signal according to a value of a select signal; and a reset circuit responsive to a direction of a transition of the select signal to generate a first reset signal in response to a first direction of the transition and to generate a second reset signal in response to a second direction of the transition, the first and second reset signals coupled to reset, respectively, a first and a second portion of the glitchless switching circuit.

13. The integrated circuit as recited in claim 12 wherein the glitchless switching circuit is operable to switch from using one of the first and second clock signals to using another of the first and second clock signals to generate the output clock signal according to the transition of the select signal.

14. The integrated circuit as recited in claim 12 wherein the reset circuit further comprises a filter circuit to generate a filtered clock signal from one of the first and second clock signals selected according to the value of the select signal.

15. The integrated circuit as recited in claim 14 wherein the filter circuit is a ripple counter.

16. The integrated circuit as recited in claim 14 wherein the reset circuit further comprises a multiplexer coupled to receive the first and second clocks and supply a selected clock signal to the filter circuit according to the select signal.

17. The integrated circuit as recited in claim 14 wherein the reset circuit further comprises: a resampling circuit to resample the select signal using the filtered clock signal; and an edge detect circuit coupled to the resampling circuit to detect the transition of the select signal.

18. The integrated circuit as recited in claim 17 wherein the edge detect circuit is responsive to the first direction of the transition to create a first pulse signal as the first reset signal and is responsive to the second direction of the transition to generate a second pulse signal as the second reset signal.

19. The integrated circuit as recited in claim 14 wherein the first portion of the glitchless switching circuit includes a first and a second flip-flop and the second portion includes a third and fourth flip-flop, wherein the first and second flip-flop have respective reset inputs coupled to the first reset signal and the third and fourth flip-flops have respective reset inputs coupled to the second reset signal.

20. A method comprising: receiving a select signal indicating to switch from generating an output clock signal in a glitchless switching circuit using a first received clock signal to generating the output clock signal using a second received clock signal; generating a first reset signal responsive to a transition of the select signal being in a first direction to reset a first path used for one of the first and second clock signals in the glitchless switching circuit; generating a second reset signal responsive to the transition of the select signal being in a second direction to reset a second path used for another of the first and second clock signals in the glitchless switching circuit.