Phase Interpolator

1. A phase interpolator comprising: a first plurality of digital-to-analog converters coupled to receive a first phase of a clock signal; a second plurality of digital-to-analog converters coupled to receive a second phase of the clock signal; a third plurality of digital-to-analog converters coupled to both the first phase of the clock signal and the second phase of the clock; wherein each digital-to-analog converter of the third plurality of digital-to-analog converters is configurable to receive either the first phase of the clock signal or the second phase of the clock signal; and a control circuit coupled to generate control signals for the third plurality of digital-to-analog converters based upon a phase code associated with a phase of an output clock signal, wherein the control signals configure digital-to-analog converters of the third plurality of digital-to-analog converters to receive either the first phase of the clock signal or the second phase of the clock signal.

2. The phase interpolator of claim 1 wherein the first plurality of digital-to-analog converters comprises a first fixed number of digital-to-analog converters and the second plurality of digital-to-analog converters comprises a second fixed number of digital-to-analog converters.

3. The phase interpolator of claim 1 wherein a first number of digital-to-analog converters of the third plurality of digital-to-analog converters is configured to receive the first phase of the clock signal and a second number of digital-to-analog converters is configured to receive the second phase of the clock signal based upon the phase of the output clock signal.

4. The phase interpolator of claim 1 wherein each digital-to-analog converter of the third plurality of digital-to-analog converters receives a control signal which selects either the first phase of the clock signal or the second phase of the clock signal.

5. The phase interpolator of claim 1 wherein each of the first plurality of digital-to-analog converters and the second plurality of digital-to-analog converters is coupled to receive a common mode input and a control signal which selects either a phase of the clock signal or a common mode signal.

6. The phase interpolator of claim 1 wherein each digital-to-analog converter of the third plurality of digital-to-analog converters comprises a first stage which determines whether the first phase or the second phase of the clock signal is selected to generate the output clock signal.

7. The phase interpolator of claim 6 wherein each digital-to-analog converter of the third plurality of analog-to-digital converters comprises a second stage which determines a sign of an output of the first stage.

8. A phase interpolator comprising: a plurality of digital-to-analog converters; and a control circuit coupled to the plurality of digital-to-analog converters; wherein a portion of the plurality of digital-to-analog converters are coupled to receive control signals, based upon a phase code associated with a phase of an output clock signal, from the control circuit which enable receiving, for each digital-to-analog converter of the portion of digital-to-analog converters, either a first phase of a clock signal or a second phase of the clock signal.

9. The phase interpolator of claim 8 wherein each digital-to-analog converter of the portion of digital-to-analog converters comprises a first stage which determines a phase of the clock signal that is selected to generate the output clock signal.

10. The phase interpolator of claim 9 wherein each digital-to-analog converter of the portion of digital-to-analog converters comprises a constant voltage bias circuit providing a constant voltage bias signal to the first stage of the digital-to-analog converter.

11. The phase interpolator of claim 9 wherein each digital-to-analog converter of the portion of digital-to-analog converters comprises a second stage which determines a sign of an output of the first stage.

12. The phase interpolator of claim 11 further comprising, for each digital-to-analog converter of the portion of digital-to-analog converters, a second constant voltage bias circuit coupled to the second stage of the digital-to-analog circuit, the second constant voltage bias circuit enabling a control transistor of the second stage to maintain a constant voltage drop across a gate and a drain of a switching transistor.

13. The phase interpolator of claim 8 wherein each digital-to-analog converter of a second portion of digital-to-analog converters is coupled to receive a common mode input.

14. The phase interpolator of claim 13 wherein each digital-to-analog converter of the second portion of digital-to-analog converters receives a control signal which selects either a phase of the clock signal or a common mode signal.

15. A method of implementing a phase interpolator, the method comprising: coupling a first phase of a clock signal to a first plurality of digital-to-analog converters; coupling a second phase of the clock signal to a second plurality of digital-to-analog converters; and coupling both the first phase of the clock signal and the second phase of the clock to a third plurality of digital-to-analog converters, wherein each digital-to-analog converter of the third plurality of digital-to-analog converters is configurable to receive either the first phase of the clock signal or the second phase of the clock signal; and coupling a control circuit to generate control signals for the third plurality of digital-to-analog converters based upon a phase code associated with a phase of an output clock signal, wherein the control signals configure digital-to-analog converters of the third plurality of digital-to-analog converters to receive either the first phase of the clock signal or the second phase of the clock signal.

16. The method of claim 15 wherein coupling both the first phase of the clock signal and the second phase of the clock signal to a third plurality of digital-to-analog converters comprises configuring a first number of digital-to-analog converters of the third plurality of digital-to-analog converters to receive the first phase of the clock signal based upon the phase of the output clock signal.

17. The method of claim 15 wherein coupling both the first phase of the clock signal and the second phase of the clock to a third plurality of digital-to-analog converters comprises configuring a second number of digital-to-analog converters of the third plurality of digital-to-analog converters to receive the second phase of the clock signal based upon the phase of the output clock signal.

18. The method of claim 15 further comprising coupling a common mode input to each of the first plurality of digital-to-analog converters and the second plurality of digital-to-analog converters.

19. The method of claim 15 further comprising selecting, for each digital-to-analog converter of the third plurality of digital-to-analog converters, either the first phase or the second phase of the clock signal using a first stage.

20. The method of claim 19 further comprising determining, for each digital-to-analog converter of the third plurality of digital-to-analog converters, a sign of an output of the first stage using a second stage.