Synchronizing A Translation Lookaside Buffer with Page Tables

1. A method for maintaining synchronization between an address translation cache of a processor and a guest page table in a virtualized computer system, in which guest software maintains the guest page table containing address translations from guest virtual addresses to guest physical addresses, and virtualization software maintains a second page table containing address translations from guest physical addresses to machine addresses, the processor using the guest page table and the second page table to determine translations from guest virtual addresses to machine addresses, the method comprising: marking entries in the second page table that map to guest page table pages to indicate that the entries map to guest page table pages, wherein the second page table contains address translations from guest physical addresses to machine addresses; modifying the contents of the address translation cache to ensure that, upon an attempt by guest software to write to a guest page table page, the processor refers to the second page table to determine the machine address of the guest page table page, instead of using a cached address translation to determine the machine address of the guest page table page; and upon a write by guest software to a memory page and as a synchronous programmatic response thereto, if the processor refers to the second page table to determine a machine address for the memory page, determining whether the entry in the second page table that contains the machine address for the memory page indicates that the memory page is a guest page table page, and, if the memory page is a guest page table page, modifying the contents of the address translation cache to eliminate an inconsistency between the address translation cache and the guest page table caused by the write to the guest page table page.

2. The method of claim 1 , wherein the address translation cache is a Translation Lookaside Buffer (TLB).

3. The method of claim 2 , wherein the TLB contains address translations from guest virtual addresses to machine addresses.

4. The method of claim 1 , wherein the second page table is one of an extended page table or a nested page table.

5. The method of claim 1 , wherein the step of marking entries to indicate that the entries map to guest page table pages comprises setting T bits in the entries.

6. The method of claim 1 , wherein the step of marking entries to indicate that the entries map to guest page table pages is performed in conjunction with performing walks of the second page table by a memory management unit of the processor.

7. The method of claim 1 , wherein the step of modifying the contents of the address translation cache to ensure that the processor refers to the second page table to determine the machine address of the guest page table page is performed in conjunction with performing walks of the second page table by a memory management unit of the processor.

8. The method of claim 1 , wherein the step of modifying the contents of the address translation cache to ensure that the processor refers to the second page table to determine the machine address of the guest page table page comprises invalidating one or more entries in the address translation cache.

9. The method of claim 1 , wherein the step of modifying the contents of the address translation cache to ensure that the processor refers to the second page table to determine the machine address of the guest page table page comprises marking one or more entries in the address translation cache as read only.

10. The method of claim 1 , wherein the step of modifying the contents of the address translation cache to eliminate an inconsistency between the address translation cache and the guest page table comprises invalidating one or more entries in the address translation cache.

11. The method of claim 1 , wherein the step of modifying the contents of the address translation cache to eliminate an inconsistency between the address translation cache and the guest page table is performed under the control of the virtualization software.

12. The method of claim 1 , further comprising, upon the write by guest software to the memory page, if the memory page is a guest page table page, clearing one or more of the entries in the second page table that map to the guest page table page so as not to indicate that the entries map to the guest page table page.

13. A method for maintaining synchronization between an address translation cache of a processor and a guest page table in a virtualized computer system, in which guest software maintains the guest page table containing address translations from guest virtual addresses to guest physical addresses, and virtualization software maintains a second page table containing address translations from guest physical addresses to machine addresses, the processor using the guest page table and the second page table to determine translations from guest virtual addresses to machine addresses, the method comprising: marking entries in the second page table that map to guest page table pages to indicate that the entries map to guest page table pages, wherein the second page table contains address translations from guest physical addresses to machine addresses; marking entries in the address translation cache that map to guest page table pages to indicate that the entries map to guest page table pages; and upon a write by guest software to a memory page and as a synchronous programmatic response thereto, if the processor refers to the address translation cache to determine a machine address for the memory page, determining whether the entry in the address translation cache that contains the machine address for the memory page indicates that the memory page is a guest page table page, or if the processor refers to the second page table to determine the machine address for the memory page, determining whether the entry in the second page table that contains the machine address for the memory page indicates that the memory page is a guest page table page, and, if the memory page is a guest page table page, modifying the contents of the address translation cache to eliminate an inconsistency between the address translation cache and the guest page table caused by the write to the guest page table page.

14. The method of claim 13 , wherein the steps of marking entries in the second page table and in the address translation cache to indicate that the entries map to guest page table pages are performed in conjunction with performing walks of the second page table by a memory management unit of the processor.

15. The method of claim 13 , wherein the steps of marking entries in the second page table and in the address translation cache to indicate that the entries map to guest page table pages are performed by the processor while not executing the virtualization software, and the step of modifying the contents of the address translation cache to eliminate an inconsistency between the address translation cache and the guest page table is performed under the control of the virtualization software.

16. The method of claim 13 further comprising, upon the write by guest software to the memory page, if the memory page is a guest page table page, clearing one or more of the entries in the second page table that map to the guest page table page so as not to indicate that the entries map to the guest page table page.

17. A method for maintaining synchronization between an address translation cache of a processor and a guest page table in a virtualized computer system, in which guest software maintains the guest page table containing address translations from guest virtual addresses to guest physical addresses, and virtualization software maintains a second page table containing address translations from guest physical addresses to machine addresses, the processor using the guest page table and the second page table to determine translations from guest virtual addresses to machine addresses, the method comprising: marking entries in the second page table that map to guest page table pages to indicate that the entries map to guest page table pages, wherein the second page table contains address translations from guest physical addresses to machine addresses; and upon a write by guest software to a memory page, determining whether the entry in the second page table that contains the machine address for the memory page indicates that the memory page is a guest page table page, and, if the memory page is a guest page table page, modifying the contents of the address translation cache to eliminate an inconsistency between the address translation cache and the guest page table caused by the write to the guest page table page.

18. The method of claim 17 , wherein the step of marking entries to indicate that the entries map to guest page table pages is performed in conjunction with performing walks of the second page table by a memory management unit of the processor.

19. The method of claim 17 , further comprising, upon the write by guest software to the memory page, if the memory page is a guest page table page, clearing one or more of the entries in the second page table that map to the guest page table page so as not to indicate that the entries map to the guest page table page.

20. A processor configured for use in a computer, the processor supporting operation of a virtualized computer system in which guest software maintains a guest page table containing address translations from guest virtual addresses to guest physical addresses, and virtualization software maintains a second page table containing address translations from guest physical addresses to machine addresses, the processor using the guest page table and the second page table to determine translations from guest virtual addresses to machine addresses, the processor performing a method for maintaining synchronization between an address translation cache of the processor and the guest page table, the method comprising: marking entries in the second page table that map to guest page table pages to indicate that the entries map to guest page table pages, wherein the second page table contains address translations from guest physical addresses to machine addresses; modifying the contents of the address translation cache to ensure that, upon an attempt by guest software to write to a guest page table page, the processor refers to the second page table to determine the machine address of the guest page table page, instead of using a cached address translation to determine the machine address; and upon a write by guest software to a memory page and as a synchronous programmatic response thereto, if the processor refers to the second page table to determine a machine address for the memory page, determining whether the entry in the second page table that contains the machine address for the memory page indicates that the memory page is a guest page table page, and, if the memory page is a guest page table page, modifying the contents of the address translation cache to eliminate an inconsistency between the address translation cache and the guest page table caused by the write to the guest page table page.

21. The processor of claim 20 , wherein the address translation cache is a Translation Lookaside Buffer (TLB).

22. The processor of claim 21 , wherein the TLB contains address translations from guest virtual addresses to machine addresses.

23. The processor of claim 20 , wherein the second page table is one of an extended page table or a nested page table.

24. The processor of claim 20 , wherein the step of marking entries to indicate that the entries map to guest page table pages comprises setting T bits in the entries.

25. The processor of claim 20 , wherein the step of marking entries to indicate that the entries map to guest page table pages is performed in conjunction with performing walks of the second page table by a memory management unit of the processor.

26. The processor of claim 20 , wherein the step of modifying the contents of the address translation cache to ensure that the processor refers to the second page table to determine the machine address of the guest page table page is performed in conjunction with performing walks of the second page table by a memory management unit of the processor.

27. The processor of claim 20 , wherein the step of modifying the contents of the address translation cache to ensure that the processor refers to the second page table to determine the machine address of the guest page table page comprises invalidating one or more entries in the address translation cache.

28. The processor of claim 20 , wherein the step of modifying the contents of the address translation cache to ensure that the processor refers to the second page table to determine the machine address of the guest page table page comprises marking one or more entries in the address translation cache as read only.

29. The processor of claim 20 , wherein the step of modifying the contents of the address translation cache to eliminate an inconsistency between the address translation cache and the guest page table comprises invalidating one or more entries in the address translation cache.

30. The processor of claim 20 , wherein the step of modifying the contents of the address translation cache to eliminate an inconsistency between the address translation cache and the guest page table is performed under the control of the virtualization software.

31. The processor of claim 20 , the method further comprising, upon the write by guest software to the memory page, if the memory page is a guest page table page, clearing one or more of the entries in the second page table that map to the guest page table page so as not to indicate that the entries map to the guest page table page.

32. A processor configured for use in a computer, the processor supporting operation of a virtualized computer system in which guest software maintains a guest page table containing address translations from guest virtual addresses to guest physical addresses, and virtualization software maintains a second page table containing address translations from guest physical addresses to machine addresses, the processor using the guest page table and the second page table to determine translations from guest virtual addresses to machine addresses, the processor performing a method for maintaining synchronization between an address translation cache of the processor and the guest page table, the method comprising: marking entries in the second page table that map to guest page table pages to indicate that the entries map to guest page table pages, wherein the second page table contains address translations from guest physical addresses to machine addresses; marking entries in the address translation cache that map to guest page table pages to indicate that the entries map to guest page table pages; and upon a write by guest software to a memory page and as a synchronous programmatic response thereto, if the processor refers to the address translation cache to determine a machine address for the memory page, determining whether the entry in the address translation cache that contains the machine address for the memory page indicates that the memory page is a guest page table page, or if the processor refers to the second page table to determine the machine address for the memory page, determining whether the entry in the second page table that contains the machine address for the memory page indicates that the memory page is a guest page table page, and, if the memory page is a guest page table page, modifying the contents of the address translation cache to eliminate an inconsistency between the address translation cache and the guest page table caused by the write to the guest page table page.

33. The processor of claim 32 , wherein the steps of marking entries in the second page table and in the address translation cache to indicate that the entries map to guest page table pages are performed in conjunction with performing walks of the second page table by a memory management unit of the processor.

34. The processor of claim 32 , the method further comprising, upon the write by guest software to the memory page, if the memory page is a guest page table page, clearing one or more of the entries in the second page table that map to the guest page table page so as not to indicate that the entries map to the guest page table page.

35. A processor configured for use in a computer, the processor supporting operation of a virtualized computer system in which guest software maintains a guest page table containing address translations from guest virtual addresses to guest physical addresses, and virtualization software maintains a second page table containing address translations from guest physical addresses to machine addresses, the processor using the guest page table and the second page table to determine translations from guest virtual addresses to machine addresses, the processor performing a method for maintaining synchronization between an address translation cache of the processor and the guest page table, the method comprising: marking entries in the second page table that map to guest page table pages to indicate that the entries map to guest page table pages, wherein the second page table contains address translations from guest physical addresses to machine addresses; and upon a write by guest software to a memory page and as a synchronous programmatic response thereto, determining whether the entry in the second page table that contains the machine address for the memory page indicates that the memory page is a guest page table page, and, if the memory page is a guest page table page, modifying the contents of the address translation cache to eliminate an inconsistency between the address translation cache and the guest page table caused by the write to the guest page table page.

36. The processor of claim 35 , wherein the step of marking entries to indicate that the entries map to guest page table pages is performed in conjunction with performing walks of the second page table by a memory management unit of the processor.

37. The processor of claim 35 , the method further comprising, upon the write by guest software to the memory page, if the memory page is a guest page table page, clearing one or more of the entries in the second page table that map to the guest page table page so as not to indicate that the entries map to the guest page table page.